公开(公告)号：US20080007301A1

公开(公告)日：2008-01-10

申请号：US11483319

申请日：2006-07-07

申请人： Sheng-Tsai Hsin-chu ,  Wen-Tai Wang

发明人： Sheng-Tsai Hsin-chu ,  Wen-Tai Wang

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： A level shifter includes a first inverter coupled between the second voltage and the first voltage, and a second inverter coupled between the second voltage and the first voltage, the second inverter being cross-coupled with the first inverter for latching a value therein. A first switch module is coupled between a first data storage node of the first and second inverters and an input signal swinging between the first voltage and a ground voltage. A second switch module is coupled between a second data storage node of the first and second inverters and an inverted input signal swinging between the ground voltage and the first voltage. The first and second inverters and the first and second switch modules include one or more MOS transistors with gate oxide layers of the same thickness.

公开(公告)号：US20120223767A1

公开(公告)日：2012-09-06

申请号：US13409408

申请日：2012-03-01

申请人： Wen-Tai Wang ,  Chao-Yen Huang

发明人： Wen-Tai Wang ,  Chao-Yen Huang

IPC分类号： H03K5/00

CPC分类号： H03K17/08104 ,  H03K19/00315 ,  H03K19/00361

摘要： A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.

摘要翻译： 两级后驱动电路包括控制电路，上拉单元和下拉单元。 下拉单元的第一N型晶体管和上拉单元的第一P型晶体管都连接到输出焊盘。 控制电路用于控制第一N型晶体管和第一P型晶体管。 因此，当上拉单元或下拉单元接通时，第一N型晶体管或第一P型晶体管的漏极端子和源极端子之间的电压差低于电压应力。

公开(公告)号：US20120162832A1

公开(公告)日：2012-06-28

申请号：US12978638

申请日：2010-12-27

申请人： Wen-Tai Wang ,  Ming-Jing Ho

发明人： Wen-Tai Wang ,  Ming-Jing Ho

IPC分类号： H02H9/04

CPC分类号： H01L27/0251 ,  H01L27/0285

摘要： For a multi-powered IC, an ESD protection circuit includes multiple voltage clamping circuits, each configured to provide a path for discharging an ESD transient current associated with a corresponding power supply.

摘要翻译： 对于多功率IC，ESD保护电路包括多个电压钳位电路，每个电压钳位电路被配置为提供用于放电与相应电源相关联的ESD瞬态电流的路径。

公开(公告)号：US06414534B1

公开(公告)日：2002-07-02

申请号：US09784819

申请日：2001-02-20

申请人： Wen-Tai Wang ,  Chung-Hui Chen

发明人： Wen-Tai Wang ,  Chung-Hui Chen

IPC分类号： H03L500

CPC分类号： H03K3/012 ,  H03K3/356113 ,  H03K3/356182

摘要： New level shifting circuits, one using dynamic current compensation and one using dynamic voltage equalization, are described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter input is connected to the input of the level shifting circuit to form an inverted level shifting input. A first NMOS transistor has the gate tied to the level shifting input and the source tied to ground. A first PMOS transistor has the gate tied to the level shifting output, the source tied to the high supply, and the drain tied to the first NMOS drain. A second NMOS transistor has the gate tied to the inverted level shifter input, the source tied to the ground, and the drain tied to the level shifting output. A second PMOS transistor has the gate tied to the first NMOS drain, the source tied to the high supply, and the drain is tied to the level shifting output. A third NMOS transistor has the gate tied to the first NMOS drain, v source tied to the level shifting input, and the drain tied to the level shifting output. A fourth NMOS transistor has the gate tied to the second NMOS drain, the source tied to the inverted level shifting input, and the drain tied to the first NMOS drain.

公开(公告)号：US08633737B2

公开(公告)日：2014-01-21

申请号：US13409408

申请日：2012-03-01

申请人： Wen-Tai Wang ,  Chao-Yen Huang

发明人： Wen-Tai Wang ,  Chao-Yen Huang

IPC分类号： H03B1/00

CPC分类号： H03K17/08104 ,  H03K19/00315 ,  H03K19/00361

摘要： A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.

摘要翻译： 两级后驱动电路包括控制电路，上拉单元和下拉单元。 下拉单元的第一N型晶体管和上拉单元的第一P型晶体管都连接到输出焊盘。 控制电路用于控制第一N型晶体管和第一P型晶体管。 因此，当上拉单元或下拉单元接通时，第一N型晶体管或第一P型晶体管的漏极端子和源极端子之间的电压差低于电压应力。

公开(公告)号：US06930530B1

公开(公告)日：2005-08-16

申请号：US10770268

申请日：2004-02-02

申请人： Wen-Tai Wang

发明人： Wen-Tai Wang

IPC分类号： H03K5/003 ,  H03K5/22 ,  H03K5/24 ,  H03K19/0185 ,  H03L5/00 ,  H04L25/02

CPC分类号： H03K19/018528 ,  H03K5/003 ,  H03K5/2481 ,  H04L25/0292

摘要： A receiver circuit. A reference voltage circuit is supplied with a first power supply voltage for outputting a reference voltage that is a mid-point voltage between the first power supply voltage and ground. A reference current circuit generates a first current according to the reference voltage. A receiving circuit is supplied with a second power supply voltage higher than the first power supply voltage, including a first current source for generating a second current according to the first current, and a differential amplifier circuit for generating an output signal contained within a voltage range of the first power supply voltage and centered around the mid-point voltage of the first power supply voltage according to the second current.

摘要翻译： 接收机电路。 参考电压电路被提供有第一电源电压，用于输出作为第一电源电压和地之间的中点电压的参考电压。 参考电流电路根据参考电压产生第一电流。 接收电路被提供有高于第一电源电压的第二电源电压，包括用于根据第一电流产生第二电流的第一电流源和用于产生包含在电压范围内的输出信号的差分放大器电路 的第一电源电压并且以第一电源电压的中点电压为中心，根据第二电流。

公开(公告)号：US20050168262A1

公开(公告)日：2005-08-04

申请号：US10770268

申请日：2004-02-02

申请人： Wen-Tai Wang

发明人： Wen-Tai Wang

IPC分类号： H03K5/003 ,  H03K5/22 ,  H03K5/24 ,  H03K19/0185 ,  H03L5/00 ,  H04L25/02

CPC分类号： H03K19/018528 ,  H03K5/003 ,  H03K5/2481 ,  H04L25/0292

摘要： A receiver circuit. A reference voltage circuit is supplied with a first power supply voltage for outputting a reference voltage that is a mid-point voltage between the first power supply voltage and ground. A reference current circuit generates a first current according to the reference voltage. A receiving circuit is supplied with a second power supply voltage higher than the first power supply voltage, including a first current source for generating a second current according to the first current, and a differential amplifier circuit for generating an output signal contained within a voltage range of the first power supply voltage and centered around the mid-point voltage of the first power supply voltage according to the second current.

摘要翻译： 接收机电路。 参考电压电路被提供有第一电源电压，用于输出作为第一电源电压和地之间的中点电压的参考电压。 参考电流电路根据参考电压产生第一电流。 接收电路被提供有高于第一电源电压的第二电源电压，包括用于根据第一电流产生第二电流的第一电流源和用于产生包含在电压范围内的输出信号的差分放大器电路 的第一电源电压并且以第一电源电压的中点电压为中心，根据第二电流。

公开(公告)号：US06765771B2

公开(公告)日：2004-07-20

申请号：US09887980

申请日：2001-06-22

申请人： Ming-Dou Ker ,  Hun-Hsien Chang ,  Wen-Tai Wang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang ,  Wen-Tai Wang

IPC分类号： H02H900

CPC分类号： H01L27/0262 ,  H01L29/7436 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection component with a deep-N-well structure in CMOS technology and the relevant circuit designs are proposed in this invention. The ESD protection component comprises a lateral silicon controlled rectifier (SCR) and a deep N-well. The SCR comprises a P-type layer, an N-type layer, a first N-well and a first P-well. The P-type layer is used as an anode of the SCR; the N-type layer is used as a cathode of the SCR; the first N-well is located between the P-type layer and the N-type layer and is contacted with the P-type layer; and the first P-well is contacted to the first N-well and the N-type layer. The deep N-well is located between the first P-well and the P-substrate, and is used to isolate the electric connection between the P-substrate and the first P-well. A plurality of these ESD protection components arbitrarily connected in series increases the total holding voltage of ESD protection circuit, thus preventing occurrences of latch-up.

摘要翻译： 本发明提出CMOS技术中具有深N阱结构的ESD保护元件及相关电路设计。 ESD保护组件包括侧向可控硅整流器（SCR）和深N阱。 SCR包括P型层，N型层，第一N阱和第一P阱。 P型层用作SCR的阳极; N型层用作SCR的阴极; 第一N阱位于P型层和N型层之间，并与P型层接触; 并且第一P阱与第一N阱和N型层接触。 深N阱位于第一P阱和P衬底之间，用于隔离P衬底和第一P阱之间的电连接。 串联任意连接的多个ESD保护元件增加了ESD保护电路的总保持电压，从而防止闩锁的发生。

公开(公告)号：US06576958B2

公开(公告)日：2003-06-10

申请号：US09836217

申请日：2001-04-18

申请人： Ming-Dou Ker ,  Hun-Hsien Chang ,  Wen-Tai Wang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang ,  Wen-Tai Wang

IPC分类号： H01L2362

CPC分类号： H01L27/0292 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

摘要： Novel PMOS-bound and NMOS-bound diodes for ESD protection, together with their application circuits, are disclosed in this invention. The PMOS-bound (or NMOS bound) diode has a PMOS (or an NMOS) structure. The source/drain region enclosed by the control gate of the PMOS (or NMOS) is used as an anode (or cathode) of the PMOS-bound (or NMOS-bound) diode. The base of the PMOS (or NMOS) is used as a cathode (or anode) of the PMOS-bound (or NMOS-bound) diode. The control gate prevents any shallow trench isolation region from forming beside the p-n junction of the PMOS-bound (or NMOS-bound) diode, such that the ESD sustaining level doesn't suffer from the formation of the STI regions. Furthermore, by ensuring proper bias to the control gate during an ESD event, the turn-on speed of the PMOS-bound or NMOS-bound diode can be increased, such that the overall ESD level of an IC chip is improved. By applying the PMOS-bound or NMOS-bound diode, ESD protection circuits for I/O buffer, power-rail ESD clamping circuits and whole-chip ESD protection systems are also provided.

公开(公告)号：US08970284B2

公开(公告)日：2015-03-03

申请号：US13409304

申请日：2012-03-01

申请人： Wen-Tai Wang ,  Sheng-Tsai Huang ,  Chao-Yen Huang

发明人： Wen-Tai Wang ,  Sheng-Tsai Huang ,  Chao-Yen Huang

IPC分类号： H03L5/00 ,  H03K19/0185

CPC分类号： H03K19/018521

摘要： A receiver circuit is provided which receives an external signal of high voltage and provides a corresponding internal signal of low voltage. The receiver circuit includes a voltage limiter, a level down shifter and an inverter of low operation voltage. The level down shifter has a front node and a back node, and includes a transistor with a gate and a source respectively coupled to the voltage limiter and the inverter at the front node and the back node. The voltage limiter limits level of the external signal transmitted to the front node, the level down shifter shifts down a signal of the front node by a cross voltage to generate a signal of the back node, and the inverter inverts the signal of the back node to generate the internal signal.

摘要翻译： 提供接收高电压的外部信号并提供相应的低电压内部信号的接收器电路。 接收器电路包括电压限制器，电平转换器和低工作电压的逆变器。 电平降低移位器具有前端节点和后端节点，并且包括具有分别耦合到限压器的栅极和源极以及前端节点和后节点处的逆变器的晶体管。 电压限制器限制发送到前端节点的外部信号的电平，电平降低位移器将前端节点的信号交叉电压转移，以产生后端节点的信号，并且逆变器反转后节点的信号 以产生内部信号。