Abstract:
A liquid crystal display panel and its driving circuit, manufacturing method are disclosed. The driving circuit has a first switching element. The first terminal of the first switching element is connected to one data line of the liquid crystal display panel. At the array manufacturing process stage, the control terminal of the first switching element is input a first reference voltage. The second terminal of the first switching element is connected to a first discharge circuit. During the stage to drive the liquid crystal display panel to display or to test the liquid crystal display panel, the control terminal of the first switching element is input a first control signal. The second terminal of the first switching element is input a data signal. By the aforementioned ways, it can simultaneously achieve an ESD protection and to save the panel space to be favorable for narrow frame design.
Abstract:
A liquid crystal display panel and its driving circuit, manufacturing method are disclosed. The driving circuit has a first switching element. The first terminal of the first switching element is connected to one data line of the liquid crystal display panel. At the array manufacturing process stage, the control terminal of the first switching element is input a first reference voltage. The second terminal of the first switching element is connected to a first discharge circuit. During the stage to drive the liquid crystal display panel to display or to test the liquid crystal display panel, the control terminal of the first switching element is input a first control signal. The second terminal of the first switching element is input a data signal. By the aforementioned ways, it can simultaneously achieve an ESD protection and to save the panel space to be favorable for narrow frame design.
Abstract:
An LTPS array substrate and a method for producing the same are proposed. The method includes: forming an insulating layer, a semiconductor layer, and a first positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a source and a drain of the TFT on the polycrystalline silicon layer; forming a pixel electrode on the insulating layer and part of the source; forming a plain passivation layer on a source-drain electrode layer; forming a transparent electrode layer on the plain passivation layer so that the transparent electrode layer is connected to the gate, the source, and the drain via the contact hole. The use of masks in types and numbers in the LTPS technology can be reduced. Thus, both of the processes and the production costs are reduced.
Abstract:
An LTPS array substrate and a method for producing the same are proposed. The method includes: forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a second insulating layer on the substrate of the polycrystalline silicon layer; forming a source and a drain of the TFT on the second insulating layer so that the source and the drain is electrically connected to the polycrystalline silicon layer via a contact hole. The use of masks in types and in numbers in the LTPS technology will be reduced. So, both of the processes and the production costs are reduced.
Abstract:
A liquid crystal display panel and a fan-out area thereof are provided. The fan-out area is arranged in a peripheral circuit area of the liquid crystal display panel and includes a middle wire and multiple fan-out wires arranged at two sides thereof. The middle wire and the fan-out wires each are disposed with at least one first wire pattern. Along each of directions toward the middle wire, widths of the first wire patterns of different wires are successively increased and/or lengths of the first wire patterns are successively decreased. The first wire patterns of a same wire have same width and length. Accordingly, the present invention can reduce the resistance differences among the wires in the fan-out area, color washout and non-uniform brightness caused by the resistance differences can be relieved or avoided, and is beneficial to the narrow border design of the liquid crystal display panel.
Abstract:
A deskew display panel is disclosed in present invention. The deskew display panel includes a plurality of data lines arranged in a column direction, a plurality of scanning lines perpendicular to the column direction and intersecting the data lines; a sub-pixel array including a plurality of sub-pixels arranged in array, each sub-pixel including a transistor and disposed between any two neighboring scanning lines and any two neighboring data lines; the scanning lines disposed in the sub-pixel array and parallel to each other; sub-pixels in each row including a plurality of sub-pixel sets, each sub-pixel set including two sub-pixels, the sub-pixel including the transistor, gates of the transistors connected to two neighboring scanning lines respectively, sources of the transistors connected to the same data line, and drains of the transistors connected to a liquid crystal capacitor and a storage capacitor.
Abstract:
The invention discloses a liquid crystal display device and its display panel. The display panel includes: a display region; a fan-out region, which is connected to at least one side of the display region; the fan-out region includes at least one group of fan-out wires, each group of the fan-out wires includes a plurality of wires, the wires include a first layer of metal wires and a second layer of metal wires that are disposed alternately, a part of the first layer of metal wires and the second layer of metal wires that are adjacent is overlapped. By the method above, the invention can reduce RC delay between the wires of each group of fan-out wires and improve display quality.
Abstract:
The present invention provides a liquid crystal display device. The device includes a light guide plate, a color filter substrate, an array substrate and a light shading tape. Wherein, a side wall of the concave slot is an incline slope, an edge of the color filter substrate is supported on the incline slope of the concave slot, an edge of a plastic frame is aligned with an edge of the array substrate, and a light shading tape for relatively fixing the color filter substrate and the light guide plate. The present invention can realize a narrow frame and no frame design of the liquid crystal display device. The structure of the display panel is simplified in order to simplify the manufacturing process and reduce the production cost.
Abstract:
The present invention proposes a TFT array substrate includes: a substrate; scan lines on the substrate; data lines intercrossing with the scan lines; a first insulating layer between the scan lines and the data lines; a second insulating layer on the first insulating layer and covering the data lines; a common electrode layer on the second insulating layer, comprising first holes located above the data lines. The first holes uncover the second insulating layer. The present invention decreases parasitic capacitance between the common electrode layer and data lines and between the common electrode layer and scan lines by decreasing overlaping sections between a common electrode layer and the data lines and between the common electrode layer and the scan lines. Therefore load of the data lines and the scan lines decreases, charge efficiency of the pixels increases, and display effect of an LCD panel is therefore improved.
Abstract:
An LTPS array substrate includes: a substrate on which a gate is disposed. An insulating layer and a polycrystalline silicon layer are disposed in sequence on the substrate and the gate. The insulating layer has an upper surface that is a plane. A source and a drain are disposed on the polycrystalline silicon layer and a pixel electrode is disposed on the insulating layer and a part of the drain. A plain passivation layer is disposed on the source and drain and includes a contact via formed therein at a location outside the polycrystalline silicon layer to expose a surface of one of the gate, the source, and the drain. A transparent electrode layer is disposed on the plain passivation layer to be electrically connected to the surface of the one of the gate, the source, and the drain that is exposed through the contact via.