公开(公告)号：US20070190712A1

公开(公告)日：2007-08-16

申请号：US11521639

申请日：2006-09-14

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Chung-Yuan Lee ,  Jeng-Ping Lin ,  Pei-Ing Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Chung-Yuan Lee ,  Jeng-Ping Lin ,  Pei-Ing Lee

IPC分类号： H01L21/8234

CPC分类号： H01L29/42376 ,  H01L29/66621

摘要： A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a trench having a sidewall and a bottom using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the trench to form a doped region. The semiconductor substrate underlying the trench is etched to form an extended portion. A gate insulating layer is formed on the trench and the extended portion. A trench gate is formed in the trench and the extended portion.

摘要翻译： 提供一种制造具有沟槽栅极的半导体器件的方法。 首先，提供其上具有沟槽蚀刻掩模的半导体衬底。 使用沟槽蚀刻掩模作为屏蔽，蚀刻半导体衬底以形成具有侧壁和底部的沟槽。 杂质通过沟槽掺杂到半导体衬底中以形成掺杂区域。 蚀刻沟槽下方的半导体衬底以形成延伸部分。 在沟槽和延伸部分上形成栅极绝缘层。 在沟槽和延伸部分中形成沟槽栅极。

公开(公告)号：US07446355B2

公开(公告)日：2008-11-04

申请号：US11556170

申请日：2006-11-03

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/66553 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66621 ,  H01L29/66659

摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

摘要翻译： 公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。 提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。 多个沟槽嵌入在半导体衬底的存储器阵列区域中。 每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。 非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

公开(公告)号：US20090011569A1

公开(公告)日：2009-01-08

申请号：US12211815

申请日：2008-09-17

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

IPC分类号： H01L21/76

CPC分类号： H01L29/66553 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66621 ,  H01L29/66659

摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

摘要翻译： 公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。 提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。 多个沟槽嵌入在半导体衬底的存储器阵列区域中。 每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。 非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

公开(公告)号：US20070161205A1

公开(公告)日：2007-07-12

申请号：US11556170

申请日：2006-11-03

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

IPC分类号： H01L21/76

CPC分类号： H01L29/66553 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66621 ,  H01L29/66659

摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

摘要翻译： 公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。 提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。 多个沟槽嵌入在半导体衬底的存储器阵列区域中。 每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。 非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

公开(公告)号：US07795090B2

公开(公告)日：2010-09-14

申请号：US12211815

申请日：2008-09-17

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

IPC分类号： H01L21/8242

CPC分类号： H01L29/66553 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66621 ,  H01L29/66659

摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

摘要翻译： 公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。 提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。 多个沟槽嵌入在半导体衬底的存储器阵列区域中。 每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。 非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

公开(公告)号：US20070246755A1

公开(公告)日：2007-10-25

申请号：US11696163

申请日：2007-04-03

申请人： Pei-Ing Lee ,  Chien-Li Cheng ,  Shian-Jyh Lin

发明人： Pei-Ing Lee ,  Chien-Li Cheng ,  Shian-Jyh Lin

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L27/10861 ,  H01L27/0629 ,  H01L27/10876

摘要： A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

摘要翻译： 公开了一种使用TTO多隔离件制造自对准栅极沟槽的方法。 提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。 多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。 每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。 聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

公开(公告)号：US07679137B2

公开(公告)日：2010-03-16

申请号：US11696163

申请日：2007-04-03

申请人： Pei-Ing Lee ,  Chien-Li Cheng ,  Shian-Jyh Lin

发明人： Pei-Ing Lee ,  Chien-Li Cheng ,  Shian-Jyh Lin

IPC分类号： H01L29/76 ,  H01L31/062

CPC分类号： H01L27/10861 ,  H01L27/0629 ,  H01L27/10876

摘要： A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

摘要翻译： 公开了一种使用TTO多隔离件制造自对准栅极沟槽的方法。 提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。 多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。 每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。 聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

公开(公告)号：US08044449B2

公开(公告)日：2011-10-25

申请号：US12183021

申请日：2008-07-30

申请人： Shian-Jyh Lin ,  Hung-Chang Liao ,  Meng-Hung Chen ,  Chung-Yuan Lee ,  Pei-Ing Lee

发明人： Shian-Jyh Lin ,  Hung-Chang Liao ,  Meng-Hung Chen ,  Chung-Yuan Lee ,  Pei-Ing Lee

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L27/10864 ,  H01L27/10841

摘要： A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain.

摘要翻译： 提供存储器件。 存储器件包括衬底，具有形成在衬底中的上部和下部的沟槽，形成在沟槽的下部的沟槽电容器，形成在沟槽电容器的侧壁上并且远离 衬底的顶表面，形成在衬底中用作源极/漏极的沟槽的上部侧的第一掺杂区域，形成在沟槽中并电连接到第一掺杂区域的导电层，顶部 形成在导电层上的电介质层，形成在顶部电介质层上的栅极，形成在栅极两侧和衬底上的外延层，以及形成在外延层的顶部上用作源极/漏极的第二掺杂区域。

公开(公告)号：US20080009112A1

公开(公告)日：2008-01-10

申请号：US11858703

申请日：2007-09-20

申请人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

发明人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

IPC分类号： H01L21/8242

CPC分类号： H01L29/66621 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10876

摘要： A method for forming a semiconductor memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor is formed in each trench. A protrusion is formed on each deep trench capacitor, wherein a top surface level of each protrusion is higher than that of the pad layer. Spacers are formed on sidewalls of the protrusions, and the pad layer and the substrate are etched using the spacers and the protrusions as a mask to form a recess. A recessed gate is formed in the recess.

摘要翻译： 公开了一种用于形成具有凹入栅极的半导体存储器件的方法。 提供其上具有垫层的衬底。 图案化衬垫层和衬底以形成至少两个沟槽。 在每个沟槽中形成深沟槽电容器。 在每个深沟槽电容器上形成突起，其中每个突起的顶表面水平高于焊盘层的顶表面高度。 间隔件形成在突起的侧壁上，并且使用间隔件和突起作为掩模来蚀刻衬垫层和衬底以形成凹部。 在凹部中形成凹槽。

公开(公告)号：US07592233B2

公开(公告)日：2009-09-22

申请号：US11858703

申请日：2007-09-20

申请人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

发明人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

IPC分类号： H01L21/8242

CPC分类号： H01L29/66621 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10876

摘要： A method for forming a memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor is formed in each trench. A protrusion is formed on each deep trench capacitor, wherein a top surface level of each protrusion is higher than that of the pad layer. Spacers are formed on sidewalls of the protrusions, and the pad layer and the substrate are etched using the spacers and the protrusions as a mask to form a recess. A recessed gate is formed in the recess.

摘要翻译： 公开了一种用于形成具有凹入栅极的存储器件的方法。 提供其上具有垫层的衬底。 图案化衬垫层和衬底以形成至少两个沟槽。 在每个沟槽中形成深沟槽电容器。 在每个深沟槽电容器上形成突起，其中每个突起的顶表面水平高于焊盘层的顶表面高度。 间隔件形成在突起的侧壁上，并且使用间隔件和突起作为掩模来蚀刻衬垫层和衬底以形成凹部。 在凹部中形成凹槽。