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公开(公告)号：US20120176388A1
公开(公告)日：2012-07-12
申请号：US13395536
申请日：2010-05-26
申请人： Makoto Yokoyama , Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shuji Nishi
发明人： Makoto Yokoyama , Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shuji Nishi
IPC分类号： G09G5/39
CPC分类号： G09G3/3648 , G02F1/13624 , G09G2300/043 , G09G2300/0819 , G09G2300/0852 , G09G2300/0876 , G09G2310/063 , G09G2310/08 , G09G2320/0219 , G09G2320/0247 , G09G2340/0428
摘要： In a memory liquid crystal display device, a potential of a storage capacitor line signal (CS) supplied to the CS lines (CSL(i)) are once decreased (ΔVcs) while the gate lines (GL(i)) are made simultaneously active (period t4, period t10) in the data holding period (T2), and the potential of the storage capacitor line signal (CS) is made back to its original potential while the gate lines (GL(i)) are made simultaneously inactive and the refresh output control lines (RC(i)) are made active (period t5, period t11). This reduces flicker, thereby allowing for improvement in display quality of the memory liquid crystal display device.
摘要翻译： 在存储器液晶显示装置中，提供给CS线（CSL（i））的辅助电容配线信号（CS）的电位在制作栅极线（GL（i））时一度减小（＆Dgr; Vcs） 数据保持期间（T2）中同时有效（周期t4，期间t10），并且保持电容配线信号（CS）的电位恢复到原来的电位，而同时进行栅极线（GL（i）） 并且刷新输出控制线（RC（i））被激活（时段t5，周期t11）。 这减少了闪烁，从而可以提高存储器液晶显示装置的显示质量。
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2.发明授权公开(公告)号：US09336740B2
公开(公告)日：2016-05-10
申请号：US14127525
申请日：2012-06-26
CPC分类号： G09G3/3688 , G09G3/3677 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： A shift register is disclosed which includes, at respective stages, unit circuits (11) each including (i) a flip-flop (11a) including first and second CMOS circuits and (ii) a signal generation circuit (11b) for generating an output signal (SROUTk) for the current stage with use of an output (Q, QB) of the flip-flop (11a), the shift register including a floating control circuit (11c) between a gate terminal of an output transistor (Tr7) of the signal generation circuit (11b) and a Q terminal. This makes it possible to reduce a circuit scale of a display driving circuit without causing a shift register to malfunction.
摘要翻译： 公开了一种移位寄存器，其在各个阶段包括单元电路（11），每个单元电路（11）包括（i）包括第一和第二CMOS电路的触发器（11a）和（ii）用于产生输出的信号生成电路 信号（SROUTk），其使用触发器（11a）的输出（Q，QB），所述移位寄存器包括在所述触发器（11a）的输出晶体管（Tr7）的栅极端之间的浮动控制电路（11c） 信号发生电路（11b）和Q端子。 这使得可以在不引起移位寄存器故障的情况下减小显示驱动电路的电路规模。
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3.发明申请公开(公告)号：US20140168181A1
公开(公告)日：2014-06-19
申请号：US14127525
申请日：2012-06-26
CPC分类号： G09G3/3688 , G09G3/3677 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： A shift register is disclosed which includes, at respective stages, unit circuits (11) each including (i) a flip-flop (11a) including first and second CMOS circuits and (ii) a signal generation circuit (11b) for generating an output signal (SROUTk) for the current stage with use of an output (Q, QB) of the flip-flop (11a), the shift register including a floating control circuit (11c) between a gate terminal of an output transistor (Tr7) of the signal generation circuit (11b) and a Q terminal. This makes it possible to reduce a circuit scale of a display driving circuit without causing a shift register to malfunction.
摘要翻译： 公开了一种移位寄存器，其在各个阶段包括单元电路（11），每个单元电路（11）包括（i）包括第一和第二CMOS电路的触发器（11a）和（ii）用于产生输出的信号生成电路 信号（SROUTk），其使用触发器（11a）的输出（Q，QB），所述移位寄存器包括在所述触发器（11a）的输出晶体管（Tr7）的栅极端之间的浮动控制电路（11c） 信号发生电路（11b）和Q端子。 这使得可以在不引起移位寄存器故障的情况下减小显示驱动电路的电路规模。
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公开(公告)号：US20140098016A1
公开(公告)日：2014-04-10
申请号：US14124018
申请日：2012-06-25
CPC分类号： H03K3/356104 , G09G3/3648
摘要： A flip-flop circuit (11a) includes: an input transistor (Tr19) having a gate terminal thereof connected to an SB terminal, a source terminal thereof connected to an RB terminal, and a drain terminal thereof connected to a first CMOS circuit and a second CMOS circuit; a power supply (VSS) which is connected to the first CMOS circuit or the second CMOS circuit and, when an SB signal is turned to be active, is connected to the RB terminal; and a regulator circuit (RC). With the arrangement, a compact flip-flop and a compact shift register employing the flip-flop are provided, without causing malfunction of the flip-flop and the shift register.
摘要翻译： 触发器电路（11a）包括：具有连接到SB端子的栅极端子的输入晶体管（Tr19），连接到RB端子的源极端子和连接到第一CMOS电路的漏极端子 第二CMOS电路; 连接到第一CMOS电路或第二CMOS电路的电源（VSS），当SB信号变为有效时，连接到RB端子; 和稳压电路（RC）。 通过这种布置，提供了一种紧凑型触发器和采用触发器的紧凑型移位寄存器，而不会引起触发器和移位寄存器的故障。
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公开(公告)号：US09293099B2
公开(公告)日：2016-03-22
申请号：US14124020
申请日：2012-06-25
CPC分类号： G09G3/3648 , G09G3/3655 , G09G3/3659 , G09G3/3677 , G09G2300/0426 , G09G2310/0286 , G09G2320/0219 , G11C19/28
摘要： A retention circuit (22) corresponding to each stage of a shift register is configured such that, when SROUT(k−1) is active, an input terminal of an inverter (INV1) and an output terminal of an inverter (INV2) are electrically connected to each other and an output terminal of the inverter (INV1) and an input terminal of the inverter (INV2) are connected to each other. This makes it possible to reduce a circuit scale of a display driving circuit without causing any malfunction of the display driving circuit.
摘要翻译： 对应于移位寄存器的各级的保持电路（22）被配置成当SROUT（k-1）有效时，逆变器（INV1）的输入端子和反相器（INV2）的输出端子是电气 连接到逆变器（INV1）的输出端子和逆变器（INV2）的输入端子彼此连接。 这使得可以减少显示驱动电路的电路规模而不会引起显示驱动电路的任何故障。
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公开(公告)号：US09124260B2
公开(公告)日：2015-09-01
申请号：US14124018
申请日：2012-06-25
CPC分类号： H03K3/356104 , G09G3/3648
摘要： A flip-flop circuit (11a) includes: an input transistor (Tr19) having a gate terminal thereof connected to an SB terminal, a source terminal thereof connected to an RB terminal, and a drain terminal thereof connected to a first CMOS circuit and a second CMOS circuit; a power supply (VSS) which is connected to the first CMOS circuit or the second CMOS circuit and, when an SB signal is turned to be active, is connected to the RB terminal; and a regulator circuit (RC). With the arrangement, a compact flip-flop and a compact shift register employing the flip-flop are provided, without causing malfunction of the flip-flop and the shift register.
摘要翻译： 触发器电路（11a）包括：具有连接到SB端子的栅极端子的输入晶体管（Tr19），连接到RB端子的源极端子和连接到第一CMOS电路的漏极端子 第二CMOS电路; 连接到第一CMOS电路或第二CMOS电路的电源（VSS），当SB信号变为有效时，连接到RB端子; 和稳压电路（RC）。 通过这种布置，提供了一种紧凑型触发器和采用触发器的紧凑型移位寄存器，而不会引起触发器和移位寄存器的故障。
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公开(公告)号：US08791895B2
公开(公告)日：2014-07-29
申请号：US13395536
申请日：2010-05-26
申请人： Makoto Yokoyama , Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shuji Nishi
发明人： Makoto Yokoyama , Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shuji Nishi
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G02F1/13624 , G09G2300/043 , G09G2300/0819 , G09G2300/0852 , G09G2300/0876 , G09G2310/063 , G09G2310/08 , G09G2320/0219 , G09G2320/0247 , G09G2340/0428
摘要： In a memory liquid crystal display device, a potential of a storage capacitor line signal (CS) supplied to the CS lines (CSL(i)) are once decreased (ΔVcs) while the gate lines (GL(i)) are made simultaneously active (period t4, period t10) in the data holding period (T2), and the potential of the storage capacitor line signal (CS) is made back to its original potential while the gate lines (GL(i)) are made simultaneously inactive and the refresh output control lines (RC(i)) are made active (period t5, period t11). This reduces flicker, thereby allowing for improvement in display quality of the memory liquid crystal display device.
摘要翻译： 在存储器液晶显示装置中，提供给CS线（CSL（i））的辅助电容配线信号（CS）的电位在制作栅极线（GL（i））时一度减小（＆Dgr; Vcs） 在数据保持期间（T2）中同时有效（周期t4，期间t10），并且保持电容配线信号（CS）的电位恢复到原来的电位，而同时进行栅极线（GL（i）） 并且刷新输出控制线（RC（i））被激活（时段t5，周期t11）。 这减少了闪烁，从而可以提高存储器液晶显示装置的显示质量。
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公开(公告)号：US09230496B2
公开(公告)日：2016-01-05
申请号：US13981219
申请日：2012-01-23
CPC分类号： G09G3/3648 , G09G3/3611 , G09G3/3685 , G09G2310/0297
摘要： This display device has a demultiplexer (501) formed on a liquid crystal panel, the demultiplexer including three switching elements SW1 to SW3 for time-division drive, which are connected to video signal lines SL1 to SL3. Here, the number of switching control signal lines for transmitting switching control signals GS1 to GS6 to be provided to switching elements coupled to the video signal lines is six, which is twice the number of time divisions, and switching control signals (e.g., GS1 and GS4) with the same timing are individually transmitted by two switching control signal lines, so that the number of switching elements to be coupled to the switching control signal lines as loads can be halved, resulting in reduced waveform rounding of the control signals.
摘要翻译： 该显示装置具有形成在液晶面板上的解复用器（501），该解复用器包括与视频信号线SL1〜SL3连接的三个时分驱动用开关元件SW1〜SW3。 这里，用于发送提供给耦合到视频信号线的开关元件的开关控制信号GS1至GS6的开关控制信号线的数量是时间分割数的两倍的开关控制信号线的数量和切换控制信号（例如，GS1和 GS4）通过两个开关控制信号线分别发送，从而将作为负载耦合到开关控制信号线的开关元件的数量减半，导致控制信号的减少的波形舍入。
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公开(公告)号：US20130300722A1
公开(公告)日：2013-11-14
申请号：US13981219
申请日：2012-01-23
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G3/3611 , G09G3/3685 , G09G2310/0297
摘要： This display device has a demultiplexer (501) formed on a liquid crystal panel, the demultiplexer including three switching elements SW1 to SW3 for time-division drive, which are connected to video signal lines SL1 to SL3. Here, the number of switching control signal lines for transmitting switching control signals GS1 to GS6 to be provided to switching elements coupled to the video signal lines is six, which is twice the number of time divisions, and switching control signals (e.g., GS1 and GS4) with the same timing are individually transmitted by two switching control signal lines, so that the number of switching elements to be coupled to the switching control signal lines as loads can be halved, resulting in reduced waveform rounding of the control signals.
摘要翻译： 该显示装置具有形成在液晶面板上的解复用器（501），该解复用器包括与视频信号线SL1〜SL3连接的三个时分驱动用开关元件SW1〜SW3。 这里，用于发送提供给耦合到视频信号线的开关元件的开关控制信号GS1至GS6的开关控制信号线的数量是时间分割数的两倍的开关控制信号线的数量和切换控制信号（例如GS1和 GS4）通过两个开关控制信号线分别发送，从而将作为负载耦合到开关控制信号线的开关元件的数量减半，导致控制信号的减少的波形舍入。
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公开(公告)号：US20130257846A1
公开(公告)日：2013-10-03
申请号：US13993922
申请日：2011-12-12
申请人： Eiji Matsuda , Yasushi Sasaki , Yuhichiroh Murakami , Seijirou Gyouten , Shuji Nishi , Makoto Yokoyama
发明人： Eiji Matsuda , Yasushi Sasaki , Yuhichiroh Murakami , Seijirou Gyouten , Shuji Nishi , Makoto Yokoyama
IPC分类号： G09G3/36
CPC分类号： G09G3/3618 , G09G3/3648 , G09G2300/0852 , G09G2300/0857 , G09G2300/0876
摘要： A memory-type liquid crystal display device includes transistors (N1, N2), retention electrodes (MRY), refresh output control sections (RS1), and capacitors (Cb1). In a data retention period, an electric potential of each of the retention electrodes (MRY) is changed via a corresponding one of the capacitors (Cb1) by changing an electric potential level of a retention capacitor wire signal that is supplied to a corresponding CS line (CSL(i)). Each of the refresh output control sections (RS1) receives the electric potential thus changed of a corresponding one of the retention electrodes (MRY) via the input section and controls an electric potential of a corresponding pixel electrode (PIX) in accordance with the electric potential thus changed.
摘要翻译： 记忆型液晶显示装置包括晶体管（N1，N2），保持电极（MRY），刷新输出控制部分（RS1）和电容器（Cb1）。 在数据保持期间，通过改变提供给相应的CS行的保持电容配线信号的电位电平，经由相应的一个电容器（Cb1）来改变每个保持电极（MRY）的电位 （CSL（i））。 每个刷新输出控制部分（RS1）经由输入部分接收相应的一个保持电极（MRY）所改变的电位，并根据电位控制对应的像素电极（PIX）的电位 从而改变了。
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