公开(公告)号：US06850454B2

公开(公告)日：2005-02-01

申请号：US10626643

申请日：2003-07-25

申请人： Shigehiro Kuge ,  Takeshi Hamamoto

发明人： Shigehiro Kuge ,  Takeshi Hamamoto

IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/12 ,  G11C8/00 ,  G11C11/34 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/00

CPC分类号： G11C29/832 ,  G11C7/12 ,  G11C11/4094 ,  G11C29/83 ,  G11C2207/2227

摘要： Data indicating whether a short-circuit defect exists in a memory block is programmed a fuse program circuit. In accordance with the fuse program data and a mode instruction signal, the correspondence relationship between a block select signal and a corresponding bit line isolation instruction signal is switched by a circuit that generates the bit line isolation instruction signal in a specific mode. It becomes possible to isolate the memory block in which a leakage current path exists from a corresponding sense amplifier band in a specific operation mode. Current consumption at least at a standby state is reduced.

摘要翻译： 指示存储器块中是否存在短路缺陷的数据被编程为熔丝编程电路。 根据熔丝程序数据和模式指令信号，通过在特定模式中产生位线隔离指令信号的电路来切换块选择信号和对应的位线隔离指令信号之间的对应关系。 在特定的操作模式中，可以将相应的读出放大器频带中存在泄漏电流路径的存储块隔开。 至少在备用状态下的电流消耗降低。

公开(公告)号：US06438067B2

公开(公告)日：2002-08-20

申请号：US09773637

申请日：2001-02-02

申请人： Shigehiro Kuge ,  Takeshi Hamamoto

发明人： Shigehiro Kuge ,  Takeshi Hamamoto

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  H03L7/0814 ,  H03L7/10

摘要： A DLL circuit includes a delay circuit for producing an output clock signal by delaying an input clock signal, and a phase comparator circuit for making a comparison between phases of the output and input clock signals. The delay circuit includes a plurality of delay units each having a unit delay amount changing in accordance with a drive potential level. The DLL circuit further includes a delay control circuit for controlling activation of the delay units in accordance with the result of phase comparison of the phase comparator circuit, and a drive potential control circuit for controlling the drive potential in accordance with the result of phase comparison of the phase comparator circuit.

摘要翻译： DLL电路包括用于通过延迟输入时钟信号来产生输出时钟信号的延迟电路，以及用于在输出和输入时钟信号的相位之间进行比较的相位比较器电路。 延迟电路包括多个延迟单元，每个延迟单元具有根据驱动电位电平而改变的单位延迟量。 DLL电路还包括延迟控制电路，用于根据相位比较器电路的相位比较的结果控制延迟单元的激活，以及用于根据相位比较结果控制驱动电位的驱动电位控制电路 相位比较电路。

公开(公告)号：US06414891B1

公开(公告)日：2002-07-02

申请号：US09771889

申请日：2001-01-30

申请人： Shigehiro Kuge ,  Takeshi Hamamoto

发明人： Shigehiro Kuge ,  Takeshi Hamamoto

IPC分类号： G11C700

摘要： A semiconductor memory device includes a pair of complementary data buses, capacitive element corresponding to an even-numbered address, an equalize circuit and amplifier, capacitive element corresponding to an odd-numbered address, and an equalize circuit and amplifier. The pair of complementary data buses continuously transfer even-numbered address data and odd-numbered address data read out from the memory cell array in an alternating manner. The equalize circuit corresponding to the odd-numbered address is operated when the amplifier corresponding to the even-numbered address operates whereas the equalize circuit corresponding to the even-numbered address is operated when the amplifier corresponding to the odd-numbered address operates.

公开(公告)号：US06781900B2

公开(公告)日：2004-08-24

申请号：US10234256

申请日：2002-09-05

申请人： Kiyohiro Furutani ,  Takeshi Hamamoto ,  Takashi Kubo ,  Shigehiro Kuge

发明人： Kiyohiro Furutani ,  Takeshi Hamamoto ,  Takashi Kubo ,  Shigehiro Kuge

IPC分类号： G11C2900

CPC分类号： G11C29/027 ,  G11C29/02

摘要： The semiconductor memory device has a formal mode and a test mode as operating modes. The program circuit includes a fuse element in which an address using a spare memory cell instead of a defective memory cell is programmed. The program circuit confirms a disconnection state of a fuse in a condition severer in the test mode than that in the normal mode. An anomaly is notified to outside by a detection circuit in a case where results are different between the test mode and the normal mode. In a case where a fuse is not completely blown, such a fuse can also be detected in the test mode to exclude a defective chip.

摘要翻译： 半导体存储器件具有作为工作模式的形式模式和测试模式。 该程序电路包括熔丝元件，其中使用备用存储单元而不是有缺陷存储单元的地址被编程。 程序电路确认在测试模式下比在正常模式下更严格的状态下的熔断器的断开状态。 在测试模式和正常模式之间的结果不同的情况下，通过检测电路将异常通知给外部。 在保险丝没有完全熔断的情况下，也可以在测试模式中检测这样的保险丝以排除有缺陷的芯片。

公开(公告)号：US08643105B2

公开(公告)日：2014-02-04

申请号：US12263762

申请日：2008-11-03

申请人： Takeshi Hamamoto

发明人： Takeshi Hamamoto

IPC分类号： H01L27/12

CPC分类号： H01L27/108 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/1203 ,  H01L29/7841 ,  H01L29/785

摘要： This disclosure concerns a semiconductor memory device including a semiconductor substrate; a buried insulation film provided on the semiconductor substrate; a semiconductor layer provided on the buried insulation film; a source layer and a drain layer provided in the semiconductor layer; a body region provided in the semiconductor layer between the source layer and the drain layer, and being in an electrically floating state, the body region accumulating or discharging charges to store data; a gate dielectric film provided on the body region; a gate electrode provided on the gate dielectric film; and a plate electrode facing a side surface of the body region via an insulation film, in an element isolation region.

摘要翻译： 本公开涉及包括半导体衬底的半导体存储器件; 设置在半导体衬底上的掩埋绝缘膜; 设置在所述掩埋绝缘膜上的半导体层; 设置在所述半导体层中的源极层和漏极层; 设置在所述源极层和所述漏极层之间的所述半导体层中并处于电浮动状态的体区，所述体区累积或放电以存储数据; 设置在所述身体区域上的栅极电介质膜; 设置在栅极电介质膜上的栅电极; 以及在元件隔离区域中经由绝缘膜面对主体区域的侧表面的平板电极。

公开(公告)号：US07952162B2

公开(公告)日：2011-05-31

申请号：US12541449

申请日：2009-08-14

申请人： Takeshi Hamamoto

发明人： Takeshi Hamamoto

IPC分类号： H01L21/76

CPC分类号： H01L29/7841 ,  H01L27/108 ,  H01L27/10802

摘要： A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.

摘要翻译： 本发明的一个实施例的半导体器件包括：衬底; 隔离层，其形成在形成在基板上的沟槽中，并且具有绝缘膜和导电层; 用于存储信号电荷的第一导电类型的半导体层，形成在隔离层之间并通过绝缘膜与导电层隔离; 形成在第一导电类型的半导体层下方的第二导电类型的半导体层; 以及具有形成在第一导电类型的半导体层上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极的晶体管。

公开(公告)号：US07719056B2

公开(公告)日：2010-05-18

申请号：US11687131

申请日：2007-03-16

申请人： Takeshi Hamamoto

发明人： Takeshi Hamamoto

IPC分类号： H01L27/088

CPC分类号： H01L27/108 ,  H01L21/764 ,  H01L21/84 ,  H01L27/10802 ,  H01L29/7841

摘要： This disclosure concerns a method of manufacturing a semiconductor memory device comprising forming a plurality of trenches in a semiconductor substrate; forming a semiconductor layer provided on a cavity by connecting lower spaces of the trenches to one another and closing upper openings of the trenches in a heat treatment under a hydrogen atmosphere; etching the semiconductor layer in an isolation formation area; forming an insulating film on a side surface and a bottom surface of the semiconductor layer; filling the cavity under the semiconductor layer with an electrode material; and forming a memory element on the semiconductor layer.

摘要翻译： 本公开涉及一种制造半导体存储器件的方法，包括在半导体衬底中形成多个沟槽; 通过将沟槽的下部空间彼此连接并在氢气氛下的热处理中闭合沟槽的上部开口，形成设置在空腔上的半导体层; 在隔离形成区域中蚀刻半导体层; 在半导体层的侧表面和底表面上形成绝缘膜; 用电极材料填充半导体层下面的空腔; 以及在所述半导体层上形成存储元件。

公开(公告)号：US07692963B2

公开(公告)日：2010-04-06

申请号：US11934337

申请日：2007-11-02

申请人： Tomoaki Shino ,  Akihiro Nitayama ,  Takeshi Hamamoto ,  Hideaki Aochi ,  Takashi Ohsawa ,  Ryo Fukuda

发明人： Tomoaki Shino ,  Akihiro Nitayama ,  Takeshi Hamamoto ,  Hideaki Aochi ,  Takashi Ohsawa ,  Ryo Fukuda

IPC分类号： G11C11/34

CPC分类号： G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/4099 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.

摘要翻译： 本公开涉及包括半导体层的半导体存储器件; 与所述半导体层的第一表面接触的电荷陷阱膜; 与所述半导体层的第二表面接触的栅极绝缘膜，所述第二表面与所述第一表面相对; 与电荷陷阱膜接触的背栅电极; 与栅极绝缘膜接触的栅电极; 在半导体层中形成的源极和漏极; 以及设置在所述漏极和源极之间的体区，所述体区域处于电浮置状态，其中通过改变数量来调整包括所述源极，漏极和所述栅电极的存储单元的阈值电压或漏极电流 的多数载体积聚在身体区域中，并且一定量的电荷被捕获到电荷陷阱膜中。

公开(公告)号：US07537989B2

公开(公告)日：2009-05-26

申请号：US11559347

申请日：2006-11-13

申请人： Tetsuya Nakai ,  Bong-Gyun Ko ,  Takeshi Hamamoto ,  Takashi Yamada

发明人： Tetsuya Nakai ,  Bong-Gyun Ko ,  Takeshi Hamamoto ,  Takashi Yamada

IPC分类号： H01L21/8238

CPC分类号： H01L21/76243

摘要： To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form a buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.

摘要翻译： 为了容易且准确地将用作SOI区域的基板表面与用作主体区域的基板表面冲洗，形成掩埋氧化膜，并且防止氧化膜暴露在基板表面上。 在由单晶硅构成的基板12的表面上部分地形成掩模氧化膜23之后，通过掩模氧化膜将氧离子16注入到基板的表面，并将基板退火以形成掩埋氧化膜13 在基板内。 进一步包括通过形成热生长氧化物膜21，形成比作为其上形成有掩模氧化膜的体积面的衬底表面12b更深的预定深度凹部12c的步骤，该衬底表面12b形成在用作SOI区域的衬底表面12a上 在形成掩模氧化膜的步骤和注入氧离子的步骤之间作为其上未形成掩模氧化物膜的SOI区域的衬底表面12a上。

公开(公告)号：US20080305588A1

公开(公告)日：2008-12-11

申请号：US12222143

申请日：2008-08-04

申请人： Takeshi Hamamoto ,  Akihiro Nitayama

发明人： Takeshi Hamamoto ,  Akihiro Nitayama

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate below the contact plugs.

摘要翻译： 根据本发明，提供了一种NAND型半导体存储装置，包括半导体衬底，形成在半导体衬底上的半导体层，在存储晶体管形成区域中选择性地形成在半导体衬底和半导体层之间的埋入绝缘膜， 形成在存储晶体管形成区域的半导体层上的扩散层，扩散层之间的浮体区域，形成在每个浮体区域上的第一绝缘膜，形成在第一绝缘膜上的浮栅，控制电极 形成在浮置栅电极上的第二绝缘膜和连接到分别位于存储晶体管形成区的端部的一对扩散层的接触插塞，其中位于 存储晶体管形成区域的端部连接到半导体 导体基板在接触塞下方。