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公开(公告)号：US06781900B2
公开(公告)日：2004-08-24
申请号：US10234256
申请日：2002-09-05
IPC分类号： G11C2900
CPC分类号： G11C29/027 , G11C29/02
摘要： The semiconductor memory device has a formal mode and a test mode as operating modes. The program circuit includes a fuse element in which an address using a spare memory cell instead of a defective memory cell is programmed. The program circuit confirms a disconnection state of a fuse in a condition severer in the test mode than that in the normal mode. An anomaly is notified to outside by a detection circuit in a case where results are different between the test mode and the normal mode. In a case where a fuse is not completely blown, such a fuse can also be detected in the test mode to exclude a defective chip.
摘要翻译： 半导体存储器件具有作为工作模式的形式模式和测试模式。 该程序电路包括熔丝元件，其中使用备用存储单元而不是有缺陷存储单元的地址被编程。 程序电路确认在测试模式下比在正常模式下更严格的状态下的熔断器的断开状态。 在测试模式和正常模式之间的结果不同的情况下，通过检测电路将异常通知给外部。 在保险丝没有完全熔断的情况下，也可以在测试模式中检测这样的保险丝以排除有缺陷的芯片。
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2.发明授权Semiconductor memory device performing high speed coincidence comparison operation with defective memory cell address 失效半导体存储器件执行具有缺陷存储单元地址的高速一致比较操作公开(公告)号：US06542422B1
公开(公告)日：2003-04-01
申请号：US10246455
申请日：2002-09-19
IPC分类号： G11C700
CPC分类号： G11C29/842 , G11C7/1051 , G11C11/4087 , G11C2207/107
摘要： When an inputted column address CA and a defect address are compared with each other, an preset defect address and a defect conversion address obtained by inverse conversion of the defect address are both inputted to a comparison circuit. In the comparison circuit, coincidence determination operations are performed being switched between when address conversion is applied to the column address CA and when no address conversion is applied thereto, thereby coincidence comparison can be effected without using the column address CA after an address conversion operation; therefore, a delay in a determination operation accompanying a conversion operation is canceled to perform high speed data reading.
摘要翻译： 当将输入的列地址CA和缺陷地址相互比较时，通过对缺陷地址进行逆转换而获得的预设缺陷地址和缺陷转换地址都被输入到比较电路。 在比较电路中，在将地址转换应用于列地址CA之间进行切换时，并且当不对其进行地址转换时进行重合确定操作，从而可以在地址转换操作之后不使用列地址CA来实现一致比较; 因此，取消伴随转换操作的确定操作的延迟以执行高速数据读取。
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3.发明授权Semiconductor memory device with reduced current consumption during standby state 失效半导体存储器件在待机状态下具有降低的电流消耗公开(公告)号：US06850454B2
公开(公告)日：2005-02-01
申请号：US10626643
申请日：2003-07-25
申请人： Shigehiro Kuge , Takeshi Hamamoto
发明人： Shigehiro Kuge , Takeshi Hamamoto
IPC分类号： G11C11/409 , G11C7/00 , G11C7/12 , G11C8/00 , G11C11/34 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/4091 , G11C11/4094 , G11C29/00
CPC分类号： G11C29/832 , G11C7/12 , G11C11/4094 , G11C29/83 , G11C2207/2227
摘要： Data indicating whether a short-circuit defect exists in a memory block is programmed a fuse program circuit. In accordance with the fuse program data and a mode instruction signal, the correspondence relationship between a block select signal and a corresponding bit line isolation instruction signal is switched by a circuit that generates the bit line isolation instruction signal in a specific mode. It becomes possible to isolate the memory block in which a leakage current path exists from a corresponding sense amplifier band in a specific operation mode. Current consumption at least at a standby state is reduced.
摘要翻译： 指示存储器块中是否存在短路缺陷的数据被编程为熔丝编程电路。 根据熔丝程序数据和模式指令信号，通过在特定模式中产生位线隔离指令信号的电路来切换块选择信号和对应的位线隔离指令信号之间的对应关系。 在特定的操作模式中，可以将相应的读出放大器频带中存在泄漏电流路径的存储块隔开。 至少在备用状态下的电流消耗降低。
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4.发明授权公开(公告)号：US06438067B2
公开(公告)日：2002-08-20
申请号：US09773637
申请日：2001-02-02
申请人： Shigehiro Kuge , Takeshi Hamamoto
发明人： Shigehiro Kuge , Takeshi Hamamoto
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/04 , G11C7/1072 , G11C7/22 , G11C8/18 , G11C11/4076 , H03L7/0814 , H03L7/10
摘要： A DLL circuit includes a delay circuit for producing an output clock signal by delaying an input clock signal, and a phase comparator circuit for making a comparison between phases of the output and input clock signals. The delay circuit includes a plurality of delay units each having a unit delay amount changing in accordance with a drive potential level. The DLL circuit further includes a delay control circuit for controlling activation of the delay units in accordance with the result of phase comparison of the phase comparator circuit, and a drive potential control circuit for controlling the drive potential in accordance with the result of phase comparison of the phase comparator circuit.
摘要翻译： DLL电路包括用于通过延迟输入时钟信号来产生输出时钟信号的延迟电路，以及用于在输出和输入时钟信号的相位之间进行比较的相位比较器电路。 延迟电路包括多个延迟单元，每个延迟单元具有根据驱动电位电平而改变的单位延迟量。 DLL电路还包括延迟控制电路，用于根据相位比较器电路的相位比较的结果控制延迟单元的激活，以及用于根据相位比较结果控制驱动电位的驱动电位控制电路 相位比较电路。
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公开(公告)号：US06414891B1
公开(公告)日：2002-07-02
申请号：US09771889
申请日：2001-01-30
申请人： Shigehiro Kuge , Takeshi Hamamoto
发明人： Shigehiro Kuge , Takeshi Hamamoto
IPC分类号： G11C700
摘要： A semiconductor memory device includes a pair of complementary data buses, capacitive element corresponding to an even-numbered address, an equalize circuit and amplifier, capacitive element corresponding to an odd-numbered address, and an equalize circuit and amplifier. The pair of complementary data buses continuously transfer even-numbered address data and odd-numbered address data read out from the memory cell array in an alternating manner. The equalize circuit corresponding to the odd-numbered address is operated when the amplifier corresponding to the even-numbered address operates whereas the equalize circuit corresponding to the even-numbered address is operated when the amplifier corresponding to the odd-numbered address operates.
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公开(公告)号：US6091651A
公开(公告)日：2000-07-18
申请号：US165502
申请日：1998-10-02
IPC分类号： G01R31/28 , G11C29/02 , G11C29/34 , G11C29/50 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C29/022 , G11C29/02 , G11C29/50
摘要： I/O lines in an I/O gate-sense amplifier portion are arranged in the order of IOA, /IOB, IOB, and /IOA. As a result, the potentials of adjacent I/O lines are necessarily different at the time of writing/reading the same data to/from a plurality of memory cells during a multi-bit test. Therefore, a short-circuit fault caused between adjacent I/O lines can be detected at the same time.
摘要翻译： I / O门检测放大器部分中的I / O线以IOA，/ IOB，IOB和/ IOA的顺序排列。 结果，在多位测试期间，在从多个存储单元写入/读取相同数据时，相邻I / O线的电位必然是不同的。 因此，可以同时检测相邻I / O线之间产生的短路故障。
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公开(公告)号：US5841705A
公开(公告)日：1998-11-24
申请号：US924501
申请日：1997-09-05
IPC分类号： G11C11/407 , G11C5/14 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C13/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4074 , G11C5/146
摘要： When an external RAS and external CAS are input to a RAS buffer and a CAS buffer, an internal RAS and an internal CAS are generated. The internal RAS is input to a clock generating circuit and a CBR mode determination circuit and the internal CAS is input to the CBR mode determination circuit. The clock generating circuit outputs a pump clock to first and second WL pumps upon input of internal RAS, and the first WL pump supplies charge to a Vpp power supply. If CAS is input prior to RAS during refresh operation, CBR mode determination circuit inputs a CBR mode signal to the second WL pump which supplies charge to Vpp power supply together with the first WL pump when the pump clock and the CBR mode signal is input thereto.
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公开(公告)号：US06777920B2
公开(公告)日：2004-08-17
申请号：US10247337
申请日：2002-09-20
IPC分类号： G05F140
CPC分类号： G05F1/465
摘要： The internal power-supply potential generating circuit includes a reference potential generating circuit having small dependency on an external power-supply potential and on a temperature, an MOS transistor for pull up, a level shifter producing a potential lower than a reference potential by a prescribed voltage to a first node and producing a potential lower than an internal power-supply potential by a voltage of the sum of the prescribed potential and an offset potential to a second node, and a differential amplifier bringing an MOS transistor out of conduction in response to the potential of the second node reaching the potential of the first node. Thus, the reference potential may be set lower by the offset voltage, allowing stable reference potential and internal power-supply potential to be obtained even if the external power-supply potential is lowered.
摘要翻译： 内部电源电位产生电路包括对外部电源电位和温度具有较小依赖性的参考电位产生电路，用于上拉的MOS晶体管，产生低于参考电位的电位的电平转换器 电压到第一节点，并且通过对第二节点的预定电位和偏移电位之和的电压产生低于内部电源电位的电位;以及差分放大器，使得MOS晶体管响应于 第二节点的潜力达到第一节点的潜力。 因此，即使外部电源电位降低，也可以将偏置电压设定为较低的基准电位，能够获得稳定的基准电位和内部电源电位。
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9.发明授权Clock generation circuit generating internal clock of small variation in phase difference from external clock, and semiconductor memory device including such clock generation circuit 失效时钟产生电路产生与外部时钟相位差小变化的内部时钟，以及包括这种时钟发生电路的半导体存储器件公开(公告)号：US06417715B2
公开(公告)日：2002-07-09
申请号：US09793999
申请日：2001-02-28
IPC分类号： G06F104
CPC分类号： H03L7/0805 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/133 , H03K5/135 , H03L7/07 , H03L7/0814 , H03L7/087 , H03L7/089 , H03L7/091
摘要： A clock generation circuit includes a clock input circuit receiving complementary external clocks to generate an internal clock, a variable delay circuit delaying the internal clock to generate an internal operation clock, a replica circuit further delaying the internal operation clock by a predetermined time to generate a return clock, a phase comparator directly comparing the phase where potential levels of external clocks cross with the phase of the return clock, and a delay control circuit adjusting the delay amount of the variable delay circuit according to a phase comparison result of the phase comparator.
摘要翻译： 时钟生成电路包括：时钟输入电路，接收互补的外部时钟以产生内部时钟;可变延迟电路，延迟内部时钟以产生内部操作时钟;复制电路进一步将内部操作时钟延迟预定时间，以产生 返回时钟，直接比较外部时钟的电位电平与返回时钟的相位相交的相位比较器的相位比较器，以及根据相位比较器的相位比较结果来调整可变延迟电路的延迟量的延迟控制电路。
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10.发明授权Semiconductor memory device having voltage down convertor reducing current consumption 有权具有降压转换器的半导体存储器件减少电流消耗公开(公告)号：US06262931B1
公开(公告)日：2001-07-17
申请号：US09539893
申请日：2000-03-31
IPC分类号： G11C800
摘要： A control circuit & mode register outputs a signal responsive to each command to a VDC control circuit. The VDC control circuit outputs a signal PWRUP changing the quantity of a through current Ic of a comparator stored in a VDC in response to the command. The VDC control circuit internally generates a signal of which pulse width corresponds to a prescribed delay time, in response to input of the command. Therefore, activation of each bank may not be monitored but current consumption can be reduced by preferably controlling a power supply current while minimizing the number of delay circuits and wires.
摘要翻译： 控制电路和模式寄存器将响应于每个命令的信号输出到VDC控制电路。 VDC控制电路响应于该命令输出改变存储在VDC中的比较器的直流电流Ic的信号PWRUP。 VDC控制电路根据命令的输入内部产生脉冲宽度对应于规定的延迟时间的信号。 因此，通过优选地控制电源电流同时最小化延迟电路和电线的数量，可以不监视每个组的激活，而可以减少电流消耗。
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