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    FDG synthesizer using columns
    3.
    发明授权
    FDG synthesizer using columns 失效
    FDG合成器使用列

    公开(公告)号：US5932178A

    公开(公告)日：1999-08-03

    申请号：US824566

    申请日：1997-03-26

    申请人： Shigeki Yamazaki ,  Katsuhiko Ohsaki

    发明人： Shigeki Yamazaki ,  Katsuhiko Ohsaki

    IPC分类号： B01J19/00 ,  B01J31/02 ,  B01J31/08 ,  C07H5/02 ,  C40B60/14 ,  G21C1/00 ,  G21G1/06

    CPC分类号： B01J31/0239 ,  B01J19/0046 ,  B01J31/0268 ,  B01J31/08 ,  C07H5/02 ,  B01J2219/00286 ,  B01J2219/0029 ,  B01J2219/00308 ,  B01J2219/00585 ,  B01J2219/0059 ,  B01J2219/00596 ,  B01J2219/0072 ,  B01J2531/98 ,  C40B60/14

    摘要： An FDG synthesizer, which comprises: a labeling reaction resin column comprising a column filled with a polymer-supported phase-transfer catalyst resin for trapping an �.sup.18 F! fluoride ion contained in a target water, and performing a labeling reaction between the thus trapped �.sup.18 F! fluoride ion and triflate, on the one hand, and a hydrolysis reaction vessel for receiving a reaction intermediate product obtained from the labeling reaction, and performing a hydrolysis reaction by adding a strong acidic aqueous solution or a strong alkaline aqueous solution thereto, on the other hand. The above-mentioned hydrolysis reaction vessel may be replaced with a cation-exchange resin column having a heating device and a flow rate control device of the reaction intermediate product.

    摘要翻译： 一种FDG合成仪，其包括：标记反应树脂柱，其包括填充有聚合物支持的相转移催化剂树脂的柱，用于捕获包含在目标水中的[18 F]氟化物离子，并且进行如此捕获的[ 18F]氟化物离子和三氟甲磺酸酯，以及用于接收由标记反应获得的反应中间产物的水解反应容器，并通过向其中加入强酸性水溶液或强碱性水溶液进行水解反应， 另一方面。 上述水解反应容器可以用具有加热装置和反应中间产物的流量控制装置的阳离子交换树脂柱代替。

    Apparatus and method for processing image signals
    4.
    发明授权
    Apparatus and method for processing image signals 失效
    用于处理图像信号的装置和方法

    公开(公告)号：US5663765A

    公开(公告)日：1997-09-02

    申请号：US543185

    申请日：1995-10-13

    申请人： Shusaku Matsuse ,  Katsuhiko Ohsaki

    发明人： Shusaku Matsuse ,  Katsuhiko Ohsaki

    IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  G09G5/391 ,  H04N5/66 ,  H04N7/01 ,  H04N11/20

    CPC分类号： H04N7/012 ,  H04N11/20 ,  H04N7/0105

    摘要： Interlaced image signals are converted into non-interlaced image signals and the scanning lines are also thinned out (i.e., the number of lines is reduced). Line memories L1-L5 are provided in a number (5) Corresponding to the number of horizontal scanning lines thinned out by a predetermined number of lines every number of lines determined from the total number of horizontal scanning lines of the PAL signal and that of the NTSC signal. A demultiplexer 12 selects the memories L1-L5 so that each PAL signal corresponding each of first to fifth ones of six horizontal scanning lines is stored. A selector 14 sequentially read the memories L1-L5 twice during an interval from the time when the PAL signal corresponding to the first horizontal scanning line is stored to the time from storing the PAL signal corresponding to the first horizontal scanning line but before storing the PAL signal corresponding to the seventh horizontal scanning line.

    摘要翻译： 隔行扫描图像信号被转换为非隔行图像信号，并且扫描线也被稀疏（即，线数减少）。 线路存储器L1-L5设置有数字（5），对应于从PAL信号的水平扫描行的总数和PAL信号的总数确定的每行数量的预定行数减少的水平扫描线的数量 NTSC信号。 解复用器12选择存储器L1-L5，以便存储对应于六条水平扫描行中的第一至第五行的每个PAL信号。 选择器14在从存储对应于第一水平扫描线的PAL信号的时间到存储对应于第一水平扫描行的PAL信号的时间之间的时间间隔内依次读取存储器L1-L5两次，但是在存储PAL 信号对应于第七水平扫描线。

    EEPROM and logic LSI chip including such EEPROM
    5.
    发明授权
    EEPROM and logic LSI chip including such EEPROM 失效
    EEPROM和包括这种EEPROM的逻辑LSI芯片

    公开(公告)号：US5465231A

    公开(公告)日：1995-11-07

    申请号：US239078

    申请日：1994-05-06

    申请人： Katsuhiko Ohsaki

    发明人： Katsuhiko Ohsaki

    IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

    CPC分类号： H01L27/115 ,  G11C16/0408 ,  G11C2216/10 ,  H01L27/105

    摘要： Disclosed is an EEPROM cell which can be manufactured with ease by the standard CMOS process. The EEPROM cell of the present invention has a first MOS transistor formed in a semiconductor substrate of a first conductivity type and having current conducting regions of a second conductivity type and a gate electrode, a well of a second conductivity type provided in the substrate, a plate electrode formed on the well with an insulating layer interposed therebetween, and at least one region of the first conductivity type formed in the well adjacent to the plate electrode. The gate electrode and the plate electrode are connected in common and act as a floating gate, and the well acts as a control gate.

    摘要翻译： 公开了可以通过标准CMOS工艺容易地制造的EEPROM单元。 本发明的EEPROM单元具有形成在第一导电类型的半导体衬底中的第一MOS晶体管，并且具有第二导电类型和栅电极的导电区域，设置在衬底中的第二导电类型的阱， 在阱上形成有绝缘层的平板电极，以及形成在与板电极相邻的阱中的至少一个第一导电类型的区域。 栅极电极和平板电极共同连接，作为浮动栅极，阱作为控制栅极。