利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

6 条记录 (耗时 0.019 秒)

    REEL DEVICE FOR WINDING ELONGATED BODY
    3.
    发明申请
    REEL DEVICE FOR WINDING ELONGATED BODY 审中-公开
    用于卷绕延长体的旋转装置

    公开(公告)号：US20100320304A1

    公开(公告)日：2010-12-23

    申请号：US12918434

    申请日：2008-12-26

    申请人： Kimitaka Iguchi ,  Hiroshi Yamano ,  Takuma Fukuda ,  Tadashi Hattori ,  Yoshinori Matsushita

    发明人： Kimitaka Iguchi ,  Hiroshi Yamano ,  Takuma Fukuda ,  Tadashi Hattori ,  Yoshinori Matsushita

    IPC分类号： B65H75/44 ,  H02G11/02 ,  B65H75/38

    CPC分类号： H02G11/02 ,  B65H75/38 ,  B65H75/4415 ,  B65H75/4452 ,  B65H75/4471 ,  B65H2701/33 ,  B65H2701/34

    摘要： A reel for winding an elongated body includes a rotor 30 that pivots relative to a casing, a free roller 22 located on the outer peripheral side of the rotor 30, and an inner reel section 30 formed on the inner side thereof. An elongated body is wound in one direction on the outer periphery of the inner reel section 23, and the elongated body extending from the inner reel section is reversed by a reversing roller 21, wound in the other direction on the outer periphery of the free roller 22, and pulled out to the outer periphery of the rotor. The inner reel section 23 is adapted to be pivotable relative to the rotor 30. The pivot shaft of the inner reel section 23 is placed at a position different from the position of the center axis 11 for pivoting of the rotor 30. The reel has a pivoting device for pivoting the inner reel section 23 such that the rotor 30 and the inner reel section 23 pivot in the directions opposite to each other with substantially the same angular speed.

    摘要翻译： 用于缠绕细长主体的卷轴包括相对于壳体枢转的转子30，位于转子30的外周侧的自由辊22和形成在其内侧的内卷轴部30。 细长体在内侧卷轴部23的外周沿一个方向缠绕，从内侧卷轴部延伸的细长体由反转辊21反转，沿着另一方向缠绕在自由辊的外周 22，并拉出到转子的外周。 内卷轴部分23适于相对于转子30枢转。内卷轴部分23的枢轴被布置在与中心轴线11的位置不同的位置，用于转动转子30的枢转。卷轴具有 用于枢转内卷轴部分23的枢转装置，使得转子30和内卷轴部分23以基本上相同的角速度在彼此相反的方向上枢转。

    Method of monitoring registers during emulation
    4.
    发明授权
    Method of monitoring registers during emulation 失效
    在仿真期间监控寄存器的方法

    公开(公告)号：US5872954A

    公开(公告)日：1999-02-16

    申请号：US548357

    申请日：1995-11-01

    申请人： Yoshinori Matsushita

    发明人： Yoshinori Matsushita

    IPC分类号： G06F11/22 ,  G06F11/26 ,  G06F11/36 ,  G06F9/455 ,  G06F11/30

    CPC分类号： G06F11/3652 ,  G06F11/261

    摘要： A method for reading various registers of a computer system without changing the emulator software. Address register 22, data memory I/O 30 and control register 26 surrounding D-MEM (data memory) 14 are configured as registers of a master/slave latching circuit in which serial scanning is possible, and are sequentially scanned during one scanning pass (1). Data memory I/O register 30 is connected to D-BUS (data bus) 10. External I/O registers RG1, RG2, . . . RGn are respectively connected to D-BUS (data bus) 10 and mapped in the I/O space. An IN'/OUT' instruction which can transfer data between data memory I/O register 30 and each external I/O register RG1 (i=1, 2, . . . , n) is generated.

    摘要翻译： 一种用于读取计算机系统的各种寄存器而不改变仿真器软件的方法。 地址寄存器22，数据存储器I / O 30和围绕D-MEM（数据存储器）14的控制寄存器26被配置为可以进行串行扫描的主/从锁存电路的寄存器，并且在一次扫描通过期间被顺序扫描 1）。 数据存储器I / O寄存器30连接到D-BUS（数据总线）10.外部I / O寄存器RG1，RG2，。 。 。 RGn分别连接到D-BUS（数据总线）10并映射到I / O空间。 生成可以在数据存储器I / O寄存器30和每个外部I / O寄存器RG1（i = 1,2，...，n）之间传送数据的IN'/ OUT'指令。

    Digital signal processing unit having three buses for simultaneously transmitting data on each bus
    5.
    发明授权
    Digital signal processing unit having three buses for simultaneously transmitting data on each bus 失效
    数字信号处理单元具有三条总线，用于在每条总线上同时发送数据

    公开(公告)号：US5822613A

    公开(公告)日：1998-10-13

    申请号：US547267

    申请日：1995-10-24

    申请人： Minoru Takaki ,  Yoshinori Matsushita

    发明人： Minoru Takaki ,  Yoshinori Matsushita

    IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/34 ,  G06F15/78 ,  G06F17/10 ,  G06F13/00

    CPC分类号： G06F9/30145 ,  G06F15/7857

    摘要： A digital processor enables data to be read from an external memory without losing arithmetic processing efficiency. A coefficient memory 16, a general-use memory 20, an arithmetic logic unit 26, a sum of products computer 28, a program memory 32, and a host interface circuit 34 are coupled to a data bus 10. A data memory 18, the general-use memory 20, an external memory input/output interface circuit 22, an audio/interface circuit 24, the arithmetic logic unit (ALU) 26, and the sum of products computer 28 are coupled to another data bus 12. The general-use memory 20, the external memory input/output interface circuit 22, and the arithmetic logic unit 26 are coupled to a general data bus 14.

    摘要翻译： 数字处理器使得能够从外部存储器读取数据，而不会降低算术处理效率。 系数存储器16，通用存储器20，算术逻辑单元26，乘积计算机28，程序存储器32和主机接口电路34的总和耦合到数据总线10.数据存储器18， 通用存储器20，外部存储器输入/输出接口电路22，音频/接口电路24，算术逻辑单元（ALU）26和产品计算机28的总和耦合到另一数据总线12。 使用存储器20，外部存储器输入/输出接口电路22和算术逻辑单元26耦合到通用数据总线14。

    Digital signal processor with halt state checking during self-test
    6.
    发明授权
    Digital signal processor with halt state checking during self-test 有权
    数字信号处理器在自检期间停止状态检查

    公开(公告)号：US06425102B1

    公开(公告)日：2002-07-23

    申请号：US09337291

    申请日：1999-06-21

    申请人： Yoshinori Matsushita

    发明人： Yoshinori Matsushita

    IPC分类号： G06F1130

    CPC分类号： G06F11/27

    摘要： The objective of the invention is to provide a DSP that can perform hold testing, which evaluates the halt state of the DSP core, during DSP core self-testing. DSP circuit 2 has input scheduler 8 that outputs restart signals to halt terminal HALT, which controls operation halt/restart for the of DSP core 4, when a fixed time has elapsed after operation of DSP core 4 has halted during hold testing, so the stopped DSP core 4 can be restarted. Thus, the internal state of DSP core 4 when operation restarts, can be recognized by the DSP core 4 itself, so it will be possible to implement hold testing that evaluates whether or not the DSP core 4 has correctly halted operation.

    摘要翻译： 本发明的目的是提供一种可在DSP核心自检期间执行保持测试的DSP，该测试评估DSP内核的停止状态。 DSP电路2具有输入调度器8，当在保持测试期间DSP核心4的操作已经停止之后经过固定时间时，输出重启信号以停止终端HALT，从而控制DSP核心4的操作停止/重启 DSP核心4可以重新启动。 因此，DSP核心4的内部状态在运行重新启动时，可以由DSP核心4自身识别，因此可以实现评估DSP内核4是否正确停止运行的保持测试。