公开(公告)号：US07981811B2

公开(公告)日：2011-07-19

申请号：US12508888

申请日：2009-07-24

申请人： Shigeru Mori ,  Takahiro Korenari ,  Tadahiro Matsuzaki ,  Hiroshi Tanabe

发明人： Shigeru Mori ,  Takahiro Korenari ,  Tadahiro Matsuzaki ,  Hiroshi Tanabe

IPC分类号： H01L21/31

CPC分类号： H01L29/78621 ,  H01L29/66757

摘要： A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is then implanted into the semiconductor layer via the gate insulating film, and a source region, a drain region, and an LDD region are formed. The gate insulating film is etched with dilute hydrofluoric acid. An electrode-protecting insulating film is then formed so as to cover the gate electrode, and the entire surface of the surface layer portion of the electrode-protecting insulating film is etched away using dilute hydrofluoric acid. Carrier traps introduced into the electrode-protecting insulating film and the gate insulating film are thereby removed.

摘要翻译： 在绝缘基板上形成基底层，以局部方式形成半导体层。 然后形成栅极绝缘膜以覆盖半导体层，并且栅极电极形成在栅极绝缘膜的一部分上。 然后通过栅极绝缘膜将杂质注入到半导体层中，形成源极区，漏极区和LDD区。 用稀氢氟酸蚀刻栅极绝缘膜。 然后形成电极保护绝缘膜以覆盖栅电极，并且使用稀氢氟酸腐蚀掉电极保护绝缘膜的表面层部分的整个表面。 因此，引入到电极保护绝缘膜和栅极绝缘膜中的载流子阱被去除。

公开(公告)号：US07582933B2

公开(公告)日：2009-09-01

申请号：US11483561

申请日：2006-07-11

申请人： Shigeru Mori ,  Takahiro Korenari ,  Tadahiro Matsuzaki ,  Hiroshi Tanabe

发明人： Shigeru Mori ,  Takahiro Korenari ,  Tadahiro Matsuzaki ,  Hiroshi Tanabe

IPC分类号： H01L29/772

CPC分类号： H01L29/78621 ,  H01L29/66757

摘要： A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is then implanted into the semiconductor layer via the gate insulating film, and a source region, a drain region, and an LDD region are formed. The gate insulating film is etched with dilute hydrofluoric acid. An electrode-protecting insulating film is then formed so as to cover the gate electrode, and the entire surface of the surface layer portion of the electrode-protecting insulating film is etched away using dilute hydrofluoric acid. Carrier traps introduced into the electrode-protecting insulating film and the gate insulating film are thereby removed.

摘要翻译： 在绝缘基板上形成基底层，以局部方式形成半导体层。 然后形成栅极绝缘膜以覆盖半导体层，并且栅极电极形成在栅极绝缘膜的一部分上。 然后通过栅极绝缘膜将杂质注入到半导体层中，形成源极区，漏极区和LDD区。 用稀氢氟酸蚀刻栅极绝缘膜。 然后形成电极保护绝缘膜以覆盖栅电极，并且使用稀氢氟酸腐蚀掉电极保护绝缘膜的表面层部分的整个表面。 因此，引入到电极保护绝缘膜和栅极绝缘膜中的载流子阱被去除。

公开(公告)号：US20070012924A1

公开(公告)日：2007-01-18

申请号：US11483561

申请日：2006-07-11

申请人： Shigeru Mori ,  Takahiro Korenari ,  Tadahiro Matsuzaki ,  Hiroshi Tanabe

发明人： Shigeru Mori ,  Takahiro Korenari ,  Tadahiro Matsuzaki ,  Hiroshi Tanabe

IPC分类号： H01L29/76

CPC分类号： H01L29/78621 ,  H01L29/66757

摘要： A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is then implanted into the semiconductor layer via the gate insulating film, and a source region, a drain region, and an LDD region are formed. The gate insulating film is etched with dilute hydrofluoric acid. An electrode-protecting insulating film is then formed so as to cover the gate electrode, and the entire surface of the surface layer portion of the electrode-protecting insulating film is etched away using dilute hydrofluoric acid. Carrier traps introduced into the electrode-protecting insulating film and the gate insulating film are thereby removed.

摘要翻译： 在绝缘基板上形成基底层，以局部方式形成半导体层。 然后形成栅极绝缘膜以覆盖半导体层，并且栅极电极形成在栅极绝缘膜的一部分上。 然后通过栅极绝缘膜将杂质注入到半导体层中，形成源极区，漏极区和LDD区。 用稀氢氟酸蚀刻栅极绝缘膜。 然后形成电极保护绝缘膜以覆盖栅电极，并且使用稀氢氟酸腐蚀掉电极保护绝缘膜的表面层部分的整个表面。 因此，引入到电极保护绝缘膜和栅极绝缘膜中的载流子阱被去除。

公开(公告)号：US08334553B2

公开(公告)日：2012-12-18

申请号：US13026683

申请日：2011-02-14

申请人： Shigeru Mori ,  Takahiro Korenari ,  Hiroshi Tanabe

发明人： Shigeru Mori ,  Takahiro Korenari ,  Hiroshi Tanabe

IPC分类号： H01L31/062

CPC分类号： H01L33/58 ,  H01L29/7833 ,  H01L29/78621 ,  H01L29/78633

摘要： A thin-film transistor manufactured on a transparent substrate has a structure of a top gate type crystalline silicon thin-film transistor in which a light blocking film, a base layer, a crystalline silicon film, a gate insulating film, and a gate electrode film arranged not to overlap at least a channel region are sequentially formed on the transparent substrate. The channel region has channel length L, LDD regions having LDD length d on both sides of the channel region, a source region, and a drain region are formed in the crystalline silicon film. The light blocking film is divided across the channel region. Interval x between the divided light blocking films is equal to or larger than channel length L and equal to or smaller than a sum of channel length L and a double of LDD length d (L+2d), allowing low the manufacturing cost and suppressed photo leak current.

摘要翻译： 制造在透明基板上的薄膜晶体管具有顶栅型晶体硅薄膜晶体管的结构，其中遮光膜，基底层，晶体硅膜，栅极绝缘膜和栅极电极膜 排列成不重叠的至少一个沟道区域依次形成在透明基板上。 沟道区具有沟道长度L，在晶体硅膜中形成在沟道区两侧具有LDD长度d的LDD区，源区和漏区。 遮光膜在通道区域上分开。 分割的遮光膜之间的间隔x等于或大于沟道长度L，并且等于或小于沟道长度L的和和LDD长度d（L + 2d）的两倍，从而允许低的制造成本和抑制的照片 泄漏电流。

公开(公告)号：US08242553B2

公开(公告)日：2012-08-14

申请号：US12838954

申请日：2010-07-19

申请人： Takahiro Korenari ,  Hiroshi Tanabe

发明人： Takahiro Korenari ,  Hiroshi Tanabe

IPC分类号： H01L29/76

CPC分类号： H01L27/1251 ,  H01L27/1214 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

摘要： A thin film transistor (TFT) substrate includes first and second TFTs on the same substrate. The first TFT has a feature that a lower conductive layer or a bottom gate electrode layer is provided between the substrate and a first insulating layer while an upper conductive layer or a top gate electrode layer is disposed on a second insulating layer formed on a semiconductor layer which is formed on the first insulating layer. The first conductive layer has first and second areas such that the first area overlaps with the first conductive layer without overlapping with the semiconductor layer while the second area overlaps with the semiconductor layer, and the first area is larger than the second area while the second insulating layer is thinner than the first insulating layer. The second TFT has the same configuration as the first TFT except that the gate electrode layer is eliminated.

摘要翻译： 薄膜晶体管（TFT）基板在同一基板上包括第一和第二TFT。 第一TFT具有在基板和第一绝缘层之间设置下导电层或底栅极电极层的特征，而上导电层或顶栅电极层设置在形成于半导体层上的第二绝缘层上 其形成在第一绝缘层上。 第一导电层具有第一和第二区域，使得第一区域与第一导电层重叠而不与半导体层重叠，而第二区域与半导体层重叠，并且第一区域大于第二区域，而第二绝缘层 层比第一绝缘层薄。 除了除去栅电极层之外，第二TFT具有与第一TFT相同的结构。

公开(公告)号：US07633571B2

公开(公告)日：2009-12-15

申请号：US11029405

申请日：2005-01-06

申请人： Takahiro Korenari ,  Hiroshi Tanabe ,  Nobuya Seko

发明人： Takahiro Korenari ,  Hiroshi Tanabe ,  Nobuya Seko

IPC分类号： G02F1/136

CPC分类号： G02F1/1368 ,  H01L27/12 ,  H01L29/78609 ,  H01L29/78621 ,  H01L29/78645

摘要： Recognizing the phenomenon that the film thickness of a semiconductor layer causes shift in the OFF-leak current characteristic that corresponds to back-gate voltage of a thin-film transistor, the average film thickness of a semiconductor layer is prescribed such that the shift of the OFF-leak current characteristic is reduced. Alternatively, the film thickness distribution (the ratio of the occurrence of each region having different film thickness) in the direction of the channel width of the semiconductor layer is prescribed.

摘要翻译： 认识到半导体层的膜厚导致与薄膜晶体管的背栅极电压相对应的OFF漏电流特性偏移的现象，规定半导体层的平均膜厚，使得 泄漏电流特性降低。 或者，规定半导体层的沟道宽度方向的膜厚分布（膜厚不同的区域的出现比例）。

公开(公告)号：US20050212987A1

公开(公告)日：2005-09-29

申请号：US11029405

申请日：2005-01-06

申请人： Takahiro Korenari ,  Hiroshi Tanabe ,  Nobuya Seko

发明人： Takahiro Korenari ,  Hiroshi Tanabe ,  Nobuya Seko

IPC分类号： G02F1/136 ,  G02F1/1368 ,  H01L21/336 ,  H01L27/12 ,  H01L29/786

CPC分类号： G02F1/1368 ,  H01L27/12 ,  H01L29/78609 ,  H01L29/78621 ,  H01L29/78645

摘要： Recognizing the phenomenon that the film thickness of a semiconductor layer causes shift in the OFF-leak current characteristic that corresponds to back-gate voltage of a thin-film transistor, the average film thickness of a semiconductor layer is prescribed such that the shift of the OFF-leak current characteristic is reduced. Alternatively, the film thickness distribution (the ratio of the occurrence of each region having different film thickness) in the direction of the channel width of the semiconductor layer is prescribed.

摘要翻译： 认识到半导体层的膜厚导致与薄膜晶体管的背栅极电压相对应的OFF漏电流特性偏移的现象，规定半导体层的平均膜厚，使得 泄漏电流特性降低。 或者，规定半导体层的沟道宽度方向的膜厚分布（膜厚不同的区域的出现比例）。

公开(公告)号：US06282043B1

公开(公告)日：2001-08-28

申请号：US09215336

申请日：1998-12-18

申请人： Takahiro Korenari

发明人： Takahiro Korenari

IPC分类号： G11B503

CPC分类号： G11B5/74 ,  G11B5/00 ,  G11B5/40 ,  G11B5/62 ,  G11B5/82 ,  G11B2005/001 ,  G11B2005/0016

摘要： The present invention provides a magnetic recording apparatus including a magnetic recording medium and a magneto-resistance effect (MR) element opposing to the magnetic recording medium, so that an information recorded on the magnetic recording medium is reproduced via the MR element, wherein if it is assumed that the MR element has a sheet resistance &rgr;s, the magnetic recording medium has a sheet resistance &rgr;s′, and the magnetic recording medium generates a medium magnetic field having a resistance change ratio P, then the values &rgr;s, &rgr;s′, and P are set to satisfy the relationship as follows: &rgr;s′>&rgr;s/P.

摘要翻译： 本发明提供一种包括磁记录介质和与磁记录介质相对的磁阻效应（MR）元件的磁记录装置，使得通过MR元件再现记录在磁记录介质上的信息，其中如果 假设MR元件具有薄层电阻rhos，磁记录介质具有薄层电阻rhos'，并且磁记录介质产生具有电阻变化率P的中等磁场，则rhos，rhos'和P 设定满足关系如下：rhos'> rhos / P。

公开(公告)号：US6157507A

公开(公告)日：2000-12-05

申请号：US162509

申请日：1998-09-29

申请人： Takahiro Korenari ,  Toshiyuki Okumura

发明人： Takahiro Korenari ,  Toshiyuki Okumura

IPC分类号： G11B5/00 ,  G11B5/02 ,  G11B5/09 ,  G11B5/39 ,  G11B5/455 ,  G11B20/10

CPC分类号： G11B5/455 ,  G11B5/09 ,  G11B20/10009 ,  G11B2005/0016

摘要： A performance evaluation method of an MR head whereby resolution performance of an MR head can be estimated, an isolated repreoduction wave form V(t) of the MR head is approximated by an equation V(t)=1/(1+(2t/PW50).sup.P), t denoting time difference from a timing which gives a peak value of the isolated reproduction wave form V(t), and PW50 denoting a half-peak-width where the isolated reproduction wave form V(t) shows more than 50% of the peak value. The resolution performance of the MR head is evaluated according to the order value P of the above equation which gives the most likelihood approximation of the isolated wave form, together with the half-peak-width PW50 relative to a minimum bit-interval to be reproduced by the MR head.

摘要翻译： MR头的性能评估方法，其中可以估计MR头的分辨率性能，MR头的隔离反向波形V（t）由等式V（t）= 1 /（1+（2t / PW50）P），t表示给出隔离再现波形V（t）的峰值的定时的时间差，表示隔离再现波形V（t）的半峰宽的PW50表示超过 峰值的50％。 MR头的分辨率性能根据给出孤立波形的最可能近似的上述等式的阶数值P以及相对于要再现的最小位间隔的半峰宽PW50来评估 由MR主管。

公开(公告)号：US07173593B2

公开(公告)日：2007-02-06

申请号：US10662531

申请日：2003-09-16

申请人： Masakiyo Matsumura ,  Takahiro Korenari

发明人： Masakiyo Matsumura ,  Takahiro Korenari

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G2300/0809 ,  G09G2300/0842

摘要： A liquid crystal display includes pixels arrayed in a matrix of rows and columns, scanning lines extending along the rows of the pixels, signal lines extending along the columns of the pixels, and pixel driving sections which are disposed near intersections of the scanning lines and signal lines, and each of which is controlled via one scanning line to capture a data signal on one signal line and output the data signal to one pixel. Particularly, each pixel driving section includes a memory circuit having a transistor whose gate is connected to the one signal line, and first and second storage capacitances which are charged to positive and negative power supply voltages and connected to a source and drain of the transistor to store the data signal as analog drive voltages of positive and negative polarities, respectively.

摘要翻译： 液晶显示器包括排列成行和列的矩阵的像素，沿着像素行延伸的扫描线，沿着像素的列延伸的信号线，以及设置在扫描线和信号的交叉点附近的像素驱动部分 线，并且其中的每一个通过一条扫描线控制以在一个信号线上捕获数据信号，并将数据信号输出到一个像素。 特别地，每个像素驱动部分包括具有栅极连接到一个信号线的晶体管的存储电路，以及被充电到正和负电源电压并连接到晶体管的源极和漏极的第一和第二存储电容， 将数据信号分别作为正极性和负极性的模拟驱动电压存储。