公开(公告)号：US06512709B1

公开(公告)日：2003-01-28

申请号：US10173429

申请日：2002-06-18

申请人： Shigeru Nakahara ,  Hideki Hayashi ,  Takeshi Suzuki ,  Keiichi Higeta

发明人： Shigeru Nakahara ,  Hideki Hayashi ,  Takeshi Suzuki ,  Keiichi Higeta

IPC分类号： G11C700

CPC分类号： G11C29/848 ,  G11C29/028 ,  G11C29/44 ,  G11C29/50012 ,  G11C29/787 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/1208 ,  G11C2029/4402

摘要： A semiconductor integrated circuit having therein a plurality of memories, realizing an improved yield by efficiently repairing a defective bit in a memory. This semiconductor integrated circuit has: a plurality of circuit blocks (RAM macro cells) each having an identification code coincidence detecting circuit for determining whether an input identification code coincides with a self identification code or not and a reception data latch and performing an operation according to latched data; a setting circuit capable of setting the identification code and information corresponding to the identification code and serially outputting the set information; and a control circuit capable of sequentially reading the setting information from the setting circuit, converting the setting information to parallel data, and transferring the parallel data to the plurality of circuit blocks. Each of the plurality of circuit blocks captures and holds the setting information transferred when the identification code coincidence detecting circuit determines that the input identification code and the self identification code coincide with each other.

公开(公告)号：US06445627B1

公开(公告)日：2002-09-03

申请号：US09886026

申请日：2001-06-22

申请人： Shigeru Nakahara ,  Hideki Hayashi ,  Takeshi Suzuki ,  Keiichi Higeta

发明人： Shigeru Nakahara ,  Hideki Hayashi ,  Takeshi Suzuki ,  Keiichi Higeta

IPC分类号： G11C700

CPC分类号： G11C29/848 ,  G11C29/028 ,  G11C29/44 ,  G11C29/50012 ,  G11C29/787 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/1208 ,  G11C2029/4402

摘要： A semiconductor integrated circuit can efficiently repair a defective bit in a memory and comprises a plurality of circuit blocks (RAM macro cells) each having an identification code coincidence detecting circuit for determining whether an input identification code coincides with a self identification code and a reception data latch and performing an operation according to latched data; a setting circuit capable of setting the identification code and information corresponding to the identification code and serially outputting the set information; and a control circuit capable of sequentially reading the set information from the setting circuit, converting the set information to parallel data, and transferring the parallel data to the plurality of circuit blocks. Each of the plurality of circuit blocks captures and holds the set information transferred when the identification code coincidence detecting circuit determines that the input identification code and the self identification code coincide.

摘要翻译： 半导体集成电路可以有效地修复存储器中的有缺陷的位，并且包括多个电路块（RAM宏单元），每个电路块具有识别码重合检测电路，用于确定输入的识别码是否与自身识别码和接收数据一致 锁存并根据锁存数据执行操作; 设置电路，其能够设置与识别码相对应的识别码和信息，并且串行地输出设定信息; 以及控制电路，能够从设定电路依次读取设定信息，将设定信息转换成并行数据，并将并行数据传送给多个电路块。 当识别码一致检测电路确定输入的识别码和自身识别码一致时，多个电路块中的每一个捕获并保持传送的设置信息。

公开(公告)号：US06496431B1

公开(公告)日：2002-12-17

申请号：US10173431

申请日：2002-06-18

申请人： Shigeru Nakahara ,  Hideki Hayashi ,  Takeshi Suzuki ,  Keiichi Higeta

发明人： Shigeru Nakahara ,  Hideki Hayashi ,  Takeshi Suzuki ,  Keiichi Higeta

IPC分类号： G11C700

CPC分类号： G11C29/848 ,  G11C29/028 ,  G11C29/44 ,  G11C29/50012 ,  G11C29/787 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/1208 ,  G11C2029/4402

摘要： A semiconductor integrated circuit having therein a plurality of memories, realizing an improved yield by efficiently repairing a defective bit in a memory. This semiconductor integrated circuit has: a plurality of circuit blocks (RAM macro cells) each having an identification code coincidence detecting circuit for determining whether an input identification code coincides with a self identification code or not and a reception data latch and performing an operation according to latched data; a setting circuit capable of setting the identification code and information corresponding to the identification code and serially outputting the set information; and a control circuit capable of sequentially reading the setting information from the setting circuit, converting the setting information to parallel data, and transferring the parallel data to the plurality of circuit blocks. Each of the plurality of circuit blocks captures and holds the setting information transferred when the identification code coincidence detecting circuit determines that the input identification code and the self identification code coincide with each other.

公开(公告)号：US06779144B2

公开(公告)日：2004-08-17

申请号：US09996722

申请日：2001-11-30

申请人： Hideki Hayashi ,  Keiichi Higeta ,  Shigeru Nakahara

发明人： Hideki Hayashi ,  Keiichi Higeta ,  Shigeru Nakahara

IPC分类号： G01R3128

CPC分类号： G11C29/36 ,  G01R31/319 ,  G11C29/14

摘要： A semiconductor integrated circuit device includes a test circuit including a first latch circuit for holding a test pattern input to an electronic circuit operating in accordance with a clock signal and a second latch circuit for holding the output signal of the electronic circuit corresponding to the test pattern. In the test circuit, the clock signal having a frequency higher than the noise frequency generated in the power line at the time of starting to supply the clock signal to the electronic circuit is continuously supplied to the electronic circuit and the test circuit, while at the same time performing, in accordance with the clock signal in a period longer than the period of the clock signal, the operation of inputting the test pattern to the first latch circuit and the operation of outputting the output signal held in the second latch circuit.

摘要翻译： 半导体集成电路装置包括测试电路，该测试电路包括用于保持测试图形输入到根据时钟信号工作的电子电路的第一锁存电路和用于保持对应于测试图案的电子电路的输出信号的第二锁存电路 。 在测试电路中，具有高于在开始向电子电路提供时钟信号时在电力线中产生的噪声频率的时钟信号被连续地提供给电子电路和测试电路，而在 同时根据时钟信号在比时钟信号的周期长的时间内执行向第一锁存电路输入测试图案的操作和输出保持在第二锁存电路中的输出信号的操作。

公开(公告)号：US20050013159A1

公开(公告)日：2005-01-20

申请号：US10917320

申请日：2004-08-13

申请人： Satoshi Iwahashi ,  Shigeru Nakahara ,  Takeshi Suzuki ,  Keiichi Higeta

发明人： Satoshi Iwahashi ,  Shigeru Nakahara ,  Takeshi Suzuki ,  Keiichi Higeta

IPC分类号： G11C11/419 ,  G11C7/10 ,  G11C8/16 ,  G11C11/41 ,  G11C11/417 ,  G11C11/00

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C8/16 ,  G11C11/4125

摘要： The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings. The semiconductor integrated circuit device is provided with first amplifier circuits; which include first MOSFETs of first conductivity type, which have gates provided for a plurality of bit lines to which memory cells are respectively connected, and which are respectively maintained in an off state under precharge voltages supplied to the bit lines, as read circuits of the memory cells determined as to whether memory currents flow according to the operation of selecting word lines and memory information; and which are respectively brought to operating states in association with select signals for the bit lines, and also provided with a second amplifier circuit including; a plurality of second MOSFETs of second conductivity type, which have gates respectively supplied with a plurality of amplified signals of the first amplifier circuits and which are connected in parallel configurations; and which forms an amplified signal corresponding to the amplified signals of the first amplifier circuits.

摘要翻译： 本发明提供了一种新型的半导体集成电路装置，其具有存储电路，高速存储器和大容量存储电路，能够加速和促进定时设定。 半导体集成电路器件设有第一放大电路; 其包括第一导电类型的第一MOSFET，其具有为存储单元分别连接的多个位线提供的栅极，并且分别在提供给位线的预充电电压下分别保持在截止状态，作为读取电路 存储器单元根据选择字线和存储器信息的操作确定存储器电流是否流动; 并且分别与用于位线的选择信号相关联地进入操作状态，并且还设置有第二放大器电路，其包括： 多个第二导电类型的第二MOSFET，其分别具有分别被提供有第一放大器电路的多个放大信号并且以并联配置连接的栅极; 并且其形成对应于第一放大器电路的放大信号的放大信号。

公开(公告)号：US06826109B2

公开(公告)日：2004-11-30

申请号：US10345186

申请日：2003-01-16

申请人： Shigeru Nakahara ,  Satoshi Iwahashi ,  Takeshi Suzuki ,  Keiichi Higeta ,  Kazuo Kanetani

发明人： Shigeru Nakahara ,  Satoshi Iwahashi ,  Takeshi Suzuki ,  Keiichi Higeta ,  Kazuo Kanetani

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/104

摘要： The invention provides a semiconductor integrated circuit device on which a RAM macro capable of selecting an operation mode adapted to improved ease of use, response, or low power consumption or selecting an input setup value is mounted. In a first operation mode of a RAM macro, a timing of receiving an input signal is set as a first timing. In a second operation mode, a timing of receiving an input signal is set to a second timing later than the first timing. In a semiconductor integrated circuit device including an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of the input circuit, the input circuit is activated on the basis of a first signal and the decoder circuit is activated on the basis of a second signal.

摘要翻译： 本发明提供了一种半导体集成电路装置，其上安装有能够选择适于提高易用性，易于使用或低功耗或选择输入设定值的操作模式的RAM宏。 在RAM宏的第一操作模式中，接收输入信号的定时被设置为第一定时。 在第二操作模式中，将接收输入信号的定时设置为晚于第一定时的第二定时。 在包括用于接收输入信号的输入电路和用于对输入电路的输出信号进行解码的解码器电路的半导体集成电路装置中，基于第一信号激活输入电路，并且解码器电路基于 的第二信号。

公开(公告)号：US06727532B2

公开(公告)日：2004-04-27

申请号：US10177044

申请日：2002-06-24

申请人： Takao Saotome ,  Takeshi Suzuki ,  Hiroyuki Tanaka ,  Shigeru Nakahara ,  Keiichi Higeta

发明人： Takao Saotome ,  Takeshi Suzuki ,  Hiroyuki Tanaka ,  Shigeru Nakahara ,  Keiichi Higeta

IPC分类号： H01L2710

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C2029/3202

摘要： There is provided a semiconductor integrated circuit device which has realized high speed operation, high integration density and highly efficient layout of the RAM macro, in which a memory array which is divided into four sections in the X and Y coordinates directions is disposed, a first input circuit for receiving a signal which requires optimization for a signal delay is disposed to the center of such four memory arrays, a second input circuit for receiving a data input and control signals thereof is disposed to the center of Y coordinate corresponding to the extending direction of the word line and a signal line for transferring an input signal from the external circuit of the RAM macro to the first and second input circuits is formed using an upper layer wiring for the wiring to form the memory array.

公开(公告)号：US06717877B2

公开(公告)日：2004-04-06

申请号：US10038663

申请日：2002-01-08

申请人： Takeshi Suzuki ,  Shigeru Nakahara ,  Keiichi Higeta ,  Takeshi Kusunoki

发明人： Takeshi Suzuki ,  Shigeru Nakahara ,  Keiichi Higeta ,  Takeshi Kusunoki

IPC分类号： G11C700

CPC分类号： G11C7/227 ,  G11C7/22 ,  G11C11/419 ,  G11C2207/2254 ,  G11C2207/2281

摘要： A semiconductor integrated circuit device includes a first variable delay circuit which delays a timing signal for activating a sense amplifier which is supplied with a signal read out from a memory array and amplifies the signal so that a timing difference between a dummy signal read out from a dummy memory cell and the timing signal of the sense amplifier is detected by a detection circuit to be made small in accordance with an output of the detection circuit, and a second variable delay circuit which adjusts a relative timing difference between the dummy signal and the timing signal of the sense amplifier.

摘要翻译： 半导体集成电路装置包括：第一可变延迟电路，其延迟用于激活读出放大器的定时信号，读出放大器被提供有从存储器阵列读出的信号，并放大该信号，使得从一个 根据检测电路的输出，由检测电路检测出虚拟存储单元和读出放大器的定时信号，使其变小，以及第二可变延迟电路，其调整虚拟信号与定时之间的相对定时差 感测放大器的信号。

公开(公告)号：US07012848B2

公开(公告)日：2006-03-14

申请号：US10917320

申请日：2004-08-13

申请人： Satoshi Iwahashi ,  Shigeru Nakahara ,  Takeshi Suzuki ,  Keiichi Higeta

发明人： Satoshi Iwahashi ,  Shigeru Nakahara ,  Takeshi Suzuki ,  Keiichi Higeta

IPC分类号： G11C7/00

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C8/16 ,  G11C11/4125

摘要： The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings. The semiconductor integrated circuit device is provided with first amplifier circuits; which include first MOSFETs of first conductivity type, which have gates provided for a plurality of bit lines to which memory cells are respectively connected, and which are respectively maintained in an off state under precharge voltages supplied to the bit lines, as read circuits of the memory cells determined as to whether memory currents flow according to the operation of selecting word lines and memory information; and which are respectively brought to operating states in association with select signals for the bit lines, and also provided with a second amplifier circuit including; a plurality of second MOSFETs of second conductivity type, which have gates respectively supplied with a plurality of amplified signals of the first amplifier circuits and which are connected in parallel configurations; and which forms an amplified signal corresponding to the amplified signals of the first amplifier circuits.

公开(公告)号：US06795368B2

公开(公告)日：2004-09-21

申请号：US10734249

申请日：2003-12-15

申请人： Satoshi Iwahashi ,  Shigeru Nakahara ,  Takeshi Suzuki ,  Keiichi Higeta

发明人： Satoshi Iwahashi ,  Shigeru Nakahara ,  Takeshi Suzuki ,  Keiichi Higeta

IPC分类号： G11C700

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C8/16 ,  G11C11/4125

摘要： The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings. The semiconductor integrated circuit device is provided with first amplifier circuits; which include first MOSFETs of first conductivity type, which have gates provided for a plurality of bit lines to which memory cells are respectively connected, and which are respectively maintained in an off state under precharge voltages supplied to the bit lines, as read circuits of the memory cells determined as to whether memory currents flow according to the operation of selecting word lines and memory information; and which are respectively brought to operating states in association with select signals for the bit lines, and also provided with a second amplifier circuit including; a plurality of second MOSFETs of second conductivity type, which have gates respectively supplied with a plurality of amplified signals of the first amplifier circuits and which are connected in parallel configurations; and which forms an amplified signal corresponding to the amplified signals of the first amplifier circuits.