公开(公告)号：US20060064271A1

公开(公告)日：2006-03-23

申请号：US10947090

申请日：2004-09-22

申请人： Shih-Tsung Liang ,  Hsin-Chih Tai

发明人： Shih-Tsung Liang ,  Hsin-Chih Tai

IPC分类号： G06F19/00

CPC分类号： G05B19/41875 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/22

摘要： A system and method for semiconductor fabrication fault analysis. The storage device stores test records. The program module receives a study lot identity, acquires suspect fabrication issues corresponding to the study lot identity, acquires a number of comparative wafer lot identities processed by the same fabrication tool and fabrication recipe for each fabrication issue, defines the comparative wafer lot identities having the same failed cluster groups as similar failed lot identities, calculates a similarity score for each similar failed lot identity, calculates a causal score according to the similarity scores for each suspect fabrication issue, and arranges the suspect fabrication issues according to causal scores thereof.

摘要翻译： 一种用于半导体制造故障分析的系统和方法。 存储设备存储测试记录。 程序模块收到学习证件身份，获取与学习签名相对应的可疑制造问题，获取由相同制造工具处理的多个比较晶片批次标识和每个制造问题的制造配方，定义具有 相同的失败的群集群，类似失败的批次身份，计算每个类似失败的批次身份的相似性得分，根据每个嫌疑人制作问题的相似性得分计算因果分数，并根据其因果分数排列可疑制作问题。

公开(公告)号：US07031860B2

公开(公告)日：2006-04-18

申请号：US10947090

申请日：2004-09-22

申请人： Shih-Tsung Liang ,  Hsin-Chih Tai

发明人： Shih-Tsung Liang ,  Hsin-Chih Tai

IPC分类号： G01N37/00 ,  G06F19/00

CPC分类号： G05B19/41875 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/22

摘要： A system and method for semiconductor fabrication fault analysis. The storage device stores test records. The program module receives a study lot identity, acquires suspect fabrication issues corresponding to the study lot identity, acquires a number of comparative wafer lot identities processed by the same fabrication tool and fabrication recipe for each fabrication issue, defines the comparative wafer lot identities having the same failed cluster groups as similar failed lot identities, calculates a similarity score for each similar failed lot identity, calculates a causal score according to the similarity scores for each suspect fabrication issue, and arranges the suspect fabrication issues according to causal scores thereof.

摘要翻译： 一种用于半导体制造故障分析的系统和方法。 存储设备存储测试记录。 程序模块收到学习证件身份，获取与学习签名相对应的可疑制造问题，获取由相同制造工具处理的多个比较晶片批次标识和每个制造问题的制造配方，定义具有 相同的失败的群集群，类似失败的批次身份，计算每个类似失败的批次身份的相似性得分，根据每个嫌疑人制作问题的相似性得分计算因果分数，并根据其因果分数排列可疑制作问题。

公开(公告)号：US08804021B2

公开(公告)日：2014-08-12

申请号：US13288880

申请日：2011-11-03

申请人： Sohei Manabe ,  Keh-Chiang Ku ,  Vincent Venezia ,  Hsin-Chih Tai ,  Duli Mao ,  Howard E. Rhodes

发明人： Sohei Manabe ,  Keh-Chiang Ku ,  Vincent Venezia ,  Hsin-Chih Tai ,  Duli Mao ,  Howard E. Rhodes

IPC分类号： H04N3/14 ,  H04N5/335

CPC分类号： H01L27/14643 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14616 ,  H01L27/1463 ,  H01L27/14641

摘要： Techniques and mechanisms for improving full well capacity for pixel structures in an image sensor. In an embodiment, a first pixel structure of the image sensor includes an implant region, where a skew of the implant region corresponds to an implant angle, and a second pixel structure of the image sensor includes a transfer gate. In another embodiment, an offset of the implant region of the first pixel structure from the transfer gate of the second pixel structure corresponds to the implant angle.

摘要翻译： 用于提高图像传感器中像素结构的完整容量的技术和机制。 在一个实施例中，图像传感器的第一像素结构包括植入区域，其中植入区域的偏斜对应于植入角度，并且图像传感器的第二像素结构包括传输门。 在另一个实施例中，第一像素结构的注入区域与第二像素结构的传输门的偏移对应于植入角度。

公开(公告)号：US20130292751A1

公开(公告)日：2013-11-07

申请号：US13462545

申请日：2012-05-02

申请人： Gang Chen ,  Duli Mao ,  Hsin-Chih Tai

发明人： Gang Chen ,  Duli Mao ,  Hsin-Chih Tai

IPC分类号： H01L31/113 ,  H01L27/146 ,  H01L31/18

CPC分类号： H01L27/14636 ,  H01L27/14643 ,  H01L27/14689

摘要： An apparatus includes a semiconductor layer having an array of pixels arranged therein. A passivation layer is disposed proximate to the semiconductor layer over the array of pixels. A segmented etch stop layer including a plurality of etch stop layer segments is disposed proximate to the passivation layer over the array of pixels. Boundaries between each one of the plurality of etch stop layer segments are aligned with boundaries between pixels in the array of pixels.

摘要翻译： 一种装置包括其中布置有像素阵列的半导体层。 钝化层设置在像素阵列附近的半导体层附近。 包括多个蚀刻停止层段的分段蚀刻停止层设置在像素阵列附近的钝化层附近。 多个蚀刻停止层段中的每一个之间的边界与像素阵列中的像素之间的边界对准。

公开(公告)号：US08575035B2

公开(公告)日：2013-11-05

申请号：US13402674

申请日：2012-02-22

申请人： Gang Chen ,  Duli Mao ,  Hsin-Chih Tai ,  Howard E. Rhodes

发明人： Gang Chen ,  Duli Mao ,  Hsin-Chih Tai ,  Howard E. Rhodes

IPC分类号： H01L31/02 ,  H01L21/76

CPC分类号： H01L21/76229 ,  H01L27/1463 ,  H01L27/14689

摘要： A method of forming trenches in a semiconductor device includes forming an etchant barrier layer above a first portion of a semiconductor layer. A first trench is etched in a second portion of the semiconductor layer using a first etchant. The second portion of the semiconductor layer is not disposed underneath the etchant barrier layer. The etchant barrier layer is etched through using a second etchant that does not substantially etch the semiconductor layer. A second trench is etched in the first portion of the semiconductor layer using a third etchant. The third etchant also extends a depth of the first trench.

摘要翻译： 在半导体器件中形成沟槽的方法包括在半导体层的第一部分上方形成蚀刻剂阻挡层。 使用第一蚀刻剂在半导体层的第二部分中蚀刻第一沟槽。 半导体层的第二部分不设置在蚀刻剂阻挡层下方。 通过使用不基本上蚀刻半导体层的第二蚀刻剂蚀刻蚀刻剂阻挡层。 使用第三蚀刻剂在半导体层的第一部分中蚀刻第二沟槽。 第三蚀刻剂还延伸第一沟槽的深度。

公开(公告)号：US20130207212A1

公开(公告)日：2013-08-15

申请号：US13370085

申请日：2012-02-09

申请人： Duli Mao ,  Hsin-Chih Tai ,  Vincent Venezia ,  Yin Qian ,  Gang Chen ,  Howard E. Rhodes

发明人： Duli Mao ,  Hsin-Chih Tai ,  Vincent Venezia ,  Yin Qian ,  Gang Chen ,  Howard E. Rhodes

IPC分类号： H01L31/0216 ,  H01L31/18

CPC分类号： H01L27/1462 ,  H01L27/14623 ,  H01L27/1464 ,  H01L27/14685

摘要： A backside illuminated image sensor includes a semiconductor layer and a trench disposed in the semiconductor layer. The semiconductor layer has a frontside surface and a backside surface. The semiconductor layer includes a light sensing element of a pixel array disposed in a sensor array region of the semiconductor layer. The pixel array is positioned to receive external incoming light through the backside surface of the semiconductor layer. The semiconductor layer also includes a light emitting element disposed in a periphery circuit region of the semiconductor layer external to the sensor array region. The trench is disposed in the semiconductor layer between the light sensing element and the light emitting element. The trench is positioned to impede a light path between the light emitting element and the light sensing element when the light path is internal to the semiconductor layer.

摘要翻译： 背面照明图像传感器包括设置在半导体层中的半导体层和沟槽。 半导体层具有前表面和背面。 半导体层包括设置在半导体层的传感器阵列区域中的像素阵列的光感测元件。 像素阵列被定位成接收穿过半导体层的背面的外部入射光。 半导体层还包括设置在传感器阵列区域外侧的半导体层的外围电路区域中的发光元件。 沟槽设置在光感测元件和发光元件之间的半导体层中。 当光路在半导体层内部时，沟槽定位成阻碍发光元件和光感测元件之间的光路。

公开(公告)号：US20130200396A1

公开(公告)日：2013-08-08

申请号：US13367162

申请日：2012-02-06

申请人： Wei Zheng ,  Vincent Venezia ,  Hsin-Chih Tai

发明人： Wei Zheng ,  Vincent Venezia ,  Hsin-Chih Tai

IPC分类号： H01L31/0232

CPC分类号： H01L27/14623 ,  H01L27/1464

摘要： An apparatus includes a semiconductor layer, a dielectric layer, and a light prevention structure. The semiconductor layer has a front surface and a backside surface. The semiconductor layer includes a light sensing element and a periphery circuit region containing a light emitting element and not containing the light sensing element. The dielectric layer contacts at least a portion of the backside surface of the semiconductor layer. At least a portion of the light prevention structure is disposed between the light sensing element and the light emitting element. The light prevention structure is positioned to prevent light emitted by the light emitting element from reaching the light sensing element.

摘要翻译： 一种装置包括半导体层，电介质层和防光结构。 半导体层具有前表面和背面。 半导体层包括光检测元件和包含发光元件并且不包含光感测元件的外围电路区域。 电介质层与半导体层的背面的至少一部分接触。 防光结构的至少一部分设置在感光元件和发光元件之间。 防光结构被定位成防止由发光元件发射的光到达感光元件。

公开(公告)号：US20130056808A1

公开(公告)日：2013-03-07

申请号：US13227099

申请日：2011-09-07

申请人： Hsin-Chih Tai ,  Keh-Chiang Ku ,  Duli Mao ,  Vincent Venezia ,  Gang Chen

发明人： Hsin-Chih Tai ,  Keh-Chiang Ku ,  Duli Mao ,  Vincent Venezia ,  Gang Chen

IPC分类号： H01L27/146 ,  H01L31/18 ,  H01L31/113

CPC分类号： H01L27/1463

摘要： An isolation area that provides additional active area between semiconductor devices on an integrated circuit is described. In one embodiment, the invention includes a complementary metal oxide semiconductor transistor of an image sensor having a source, a drain, and a gate between the source and the drain, the transistor having a channel to couple the source and the drain under the influence of the gate, and an isolation barrier surrounding a periphery of the source and the drain to isolate the source and the drain from other devices, wherein the isolation barrier is distanced from the central portion of the channel.

摘要翻译： 描述了在集成电路上的半导体器件之间提供附加有效面积的隔离区域。 在一个实施例中，本发明包括具有在源极和漏极之间的源极，漏极和栅极的图像传感器的互补金属氧化物半导体晶体管，晶体管具有在源极和漏极之间耦合源极和漏极的沟道 栅极和围绕源极和漏极的周边的隔离屏障，以将源极和漏极与其它器件隔离，其中隔离屏障与通道的中心部分分开。

公开(公告)号：US08373243B2

公开(公告)日：2013-02-12

申请号：US12986032

申请日：2011-01-06

申请人： Hsin-Chih Tai ,  Vincent Venezia ,  Yin Qian ,  Duli Mao ,  Keh-Chiang Ku

发明人： Hsin-Chih Tai ,  Vincent Venezia ,  Yin Qian ,  Duli Mao ,  Keh-Chiang Ku

IPC分类号： H01L31/12

CPC分类号： H01L27/14643 ,  H01L27/14636 ,  H01L27/1464

摘要： A backside illuminated imaging sensor with a seal ring support includes an epitaxial layer having an imaging array formed in a front side of the epitaxial layer. A metal stack is coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of the imaging sensor. An opening is included that extends from the back side of the epitaxial layer to a metal pad of the seal ring to expose the metal pad. The seal ring support is disposed on the metal pad and within the opening to structurally support the seal ring.

摘要翻译： 具有密封环支撑件的背面照明成像传感器包括具有形成在外延层的前侧的成像阵列的外延层。 金属叠层耦合到外延层的前侧，其中金属堆叠包括形成在成像传感器的边缘区域中的密封环。 包括从外延层的背面延伸到密封环的金属焊盘以露出金属焊盘的开口。 密封环支撑件设置在金属垫上并且在开口内，以在结构上支撑密封环。

公开(公告)号：US20120319242A1

公开(公告)日：2012-12-20

申请号：US13164563

申请日：2011-06-20

申请人： Duli Mao ,  Hsin-Chih Tai ,  Vincent Venezia ,  Keh-Chiang Ku ,  Yin Qian ,  Gang Chen ,  Rongsheng Yang ,  Howard Rhodes

发明人： Duli Mao ,  Hsin-Chih Tai ,  Vincent Venezia ,  Keh-Chiang Ku ,  Yin Qian ,  Gang Chen ,  Rongsheng Yang ,  Howard Rhodes

IPC分类号： H01L29/02 ,  H01L31/02

CPC分类号： H01L21/26513 ,  H01L21/76237 ,  H01L27/1463 ,  H01L27/14689

摘要： Forming a doped isolation region in a substrate during manufacture of an image sensor. A method of an aspect includes forming a hardmask layer over the substrate, and forming a photoresist layer over the hardmask layer. An opening is formed in the photoresist layer over an intended location of the doped isolation region. An opening is etched in the hardmask layer by exposing the hardmask layer to one or more etchants through the opening. The opening in the hardmask layer may have a width of less than 0.4 micrometers. The doped isolation region may be formed in the substrate beneath the opening in the hardmask layer by performing a dopant implantation that introduces dopant through the opening in the hardmask layer. The method of an aspect may include forming sidewall spacers on sidewalls of the opening in the hardmask layer and using the sidewall spacers as a dopant implantation mask.

摘要翻译： 在图像传感器的制造期间在衬底中形成掺杂的隔离区域。 一种方面的方法包括在衬底上形成硬掩模层，以及在硬掩模层上形成光致抗蚀剂层。 在掺杂隔离区域的预定位置上的光致抗蚀剂层中形成开口。 通过将硬掩模层暴露于通过开口的一个或多个蚀刻剂，在硬掩模层中蚀刻开口。 硬掩模层中的开口可以具有小于0.4微米的宽度。 可以通过执行通过硬掩模层中的开口引入掺杂剂的掺杂剂注入，在硬掩模层中的开口下方的衬底中形成掺杂隔离区。 一方面的方法可以包括在硬掩模层中的开口的侧壁上形成侧壁间隔物，并且使用侧壁间隔物作为掺杂剂注入掩模。