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    High frequency ceramic compact, use thereof, and method of producing the same
    3.
    发明授权
    High frequency ceramic compact, use thereof, and method of producing the same 失效
    高频陶瓷压块及其制造方法

    公开(公告)号：US06549094B2

    公开(公告)日：2003-04-15

    申请号：US09874880

    申请日：2001-06-05

    申请人： Hitoshi Takagi ,  Mizuki Kono ,  Tsutomu Tatekawa

    发明人： Hitoshi Takagi ,  Mizuki Kono ,  Tsutomu Tatekawa

    IPC分类号： H01P1213

    CPC分类号： C04B35/111

    摘要： A high frequency ceramic compact includes Al, Ti and Mn as metallic elements and contains substantially no Al2TiO5 phase as determined by X-ray diffraction analysis and is obtained by firing at about 1310° C. or lower. A preferred high frequency ceramic compact is represented by the following formula and has a Q-value at 10 GHz of 10,000 or more: (100−x−y)AlO3/2−xTiO2−yMnO, wherein x and y are % by mole and x and y satisfy the following conditions: 3.0≦x≦9.0; and 0.1≦y≦1.0. These high frequency ceramic compacts have a relative dielectric constant of 20 or less, a Q-value at 10 GHz of 10,000 or more, and can optionally control the temperature coefficient of resonant frequency around 0 ppm/° C.

    摘要翻译： 高频陶瓷压块包括Al，Ti和Mn作为金属元素，并且通过X射线衍射分析确定基本上不含Al 2 TiO 5相，并且通过在约1310℃或更低温度下烧制获得。 优选的高频陶瓷压块由下式表示，并且在10GHz处具有10,000或更高的Q值：（100-xy）AlO 3/2-xTiO 2 -YMnO，其中x和y是摩尔％，x和 y满足以下条件：3.0 <= x <= 9.0; 和0.1 <= y <= 1.0。 这些高频陶瓷压块具有20或更小的相对介电常数，10GHz的Q值为10,000或更大，并且可以可选地控制谐振频率的温度系数在约0ppm /℃。

    Method of simultaneously removing sulfur dioxide and nitrogen oxides from exhaust gases
    5.
    发明授权
    Method of simultaneously removing sulfur dioxide and nitrogen oxides from exhaust gases 失效
    同时从废气中除去二氧化硫和氮氧化物的方法

    公开(公告)号：US4186176A

    公开(公告)日：1980-01-29

    申请号：US927249

    申请日：1978-07-21

    申请人： Taketsugu Kitamura ,  Hitoshi Takagi

    发明人： Taketsugu Kitamura ,  Hitoshi Takagi

    IPC分类号： B01D53/60 ,  C01B17/04 ,  B01D53/00

    CPC分类号： B01D53/60

    摘要： A method of simultaneously removing sulfur dioxide and nitrogen oxides from an exhaust gas which comprises the steps of:contacting the exhaust gas with an aqueous absorbing solution containing an iron chelate complex and an alkali metal sulfite to form alkali metal sulfur oxides comprising an alkali metal dithionate in the aqueous absorbing solution;separating the alkali metal sulfur oxides formed and accumulated from part or the whole of the aqueous absorbing solution by crystallization; andsubjecting the alkali metal sulfur oxides separated together with a carbonaceous material to decomposition-reduction reaction at a temperature of at least about 700.degree. C. to form an alkali metal sulfide and a gas comprising sulfur dioxide and carbon dioxide.

    摘要翻译： 一种同时从废气中除去二氧化硫和氮氧化物的方法，其特征在于包括以下步骤：使废气与含有铁螯合物和碱金属亚硫酸盐的吸收水溶液接触，形成碱金属硫氧化物， 在吸收水溶液中; 通过结晶分离由吸收水溶液的一部分或全部形成和积聚的碱金属硫氧化物; 并且在至少约700℃的温度下将与碳质材料一起分离的碱金属硫氧化物进行分解还原反应，以形成碱金属硫化物和包含二氧化硫和二氧化碳的气体。

    Information processing system having an address translation table loaded with main/expanded memory presence bits
    8.
    发明授权
    Information processing system having an address translation table loaded with main/expanded memory presence bits 失效
    具有加载有主/扩展存储器存在位的地址转换表的信息处理系统

    公开(公告)号：US5481688A

    公开(公告)日：1996-01-02

    申请号：US20369

    申请日：1993-02-22

    申请人： Hitoshi Takagi

    发明人： Hitoshi Takagi

    IPC分类号： G06F12/08 ,  G06F12/10

    CPC分类号： G06F12/1009

    摘要： An information processing system has a main memory unit, an expanded memory unit, and an instruction processing unit producing a virtual address. An address translation table, namely, a page table stores page table words which include main/expanded memory presence bits indicating to which memory unit of the main memory unit and the expanded memory unit real pages are stored. Preferably, the instruction processing unit may include an access type determiner for determining an access type for at least one operand. The access type indicates which memory unit is the optimum one for the operand. Instead of the access type determiner, the instruction processing unit may include segment descriptor registers for storing segment descriptors having expanded memory bits indicating which memory units are the optimum ones for the segments. In place of the access type determiner, the instruction processing unit may include virtual space registers for indicating virtual space numbers identifying a plurality of virtual spaces and an access type determining circuit for determining which memory unit is the optimum one for a designated virtual space.

    摘要翻译： 信息处理系统具有主存储单元，扩展存储器单元和产生虚拟地址的指令处理单元。 地址转换表，即页表存储包括主/扩展存储器存在位的页表字，其指示存储主存储单元和扩展存储单元实际页的哪个存储单元。 优选地，指令处理单元可以包括用于确定至少一个操作数的访问类型的访问类型确定器。 访问类型指示哪个存储单元是操作数最佳的存储单元。 代替访问类型确定器，指令处理单元可以包括用于存储具有扩展的存储器位的段描述符的段描述符寄存器，其指示哪些存储器单元是段的最佳存储器单元。 代替访问类型确定器，指令处理单元可以包括用于指示识别多个虚拟空间的虚拟空间号的虚拟空间寄存器和用于确定哪个存储器单元是指定的虚拟空间的最佳的存储单元的访问类型确定电路。

    Input/output interruption control system for a virtual machine
    9.
    发明授权
    Input/output interruption control system for a virtual machine 失效
    用于虚拟机的输入/输出中断控制系统

    公开(公告)号：US5371857A

    公开(公告)日：1994-12-06

    申请号：US955442

    申请日：1992-10-02

    申请人： Hitoshi Takagi

    发明人： Hitoshi Takagi

    IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F13/10 ,  G06F13/24 ,  G06F13/00

    CPC分类号： G06F13/24

    摘要： The input/output interruption control system comprises a plurality of instruction processors, a plurality of virtual machines, a control program for activation and control of the virtual machines, an input/output processor which activates input/output operation, and a memory (4) for interruption information storing. The instruction processor further comprises registers (53, 63) to store identifiers to identify the virtual machine currently in operation, an interruption acceptance (52, 62) to accept input/output completion interruption requests for the virtual machine currently in operation, and an interruption check (54, 64) which recognizes the existence of an input/output completion interruption request for the virtual machine in operation and activates the input/output completion interruption processing, and a notification bus (5) to send the input/output completion interruption request and the identifier of the specific virtual machine to other instruction processor when the specific virtual machine is activated. Such interruption acceptance (52, 62) of the instruction processors further comprises a input (90) to forcibly activate the interruption check (54, 64) means upon acceptance of an input/output completion interruption and identifier for the specific virtual machine from other instruction processor.

    摘要翻译： 输入/输出中断控制系统包括多个指令处理器，多个虚拟机，用于激活和控制虚拟机的控制程序，激活输入/输出操作的输入/输出处理器，以及存储器（4） 用于中断信息存储。 指令处理器还包括用于存储标识符以识别当前正在运行的虚拟机的寄存器（53,63），接受当前运行的虚拟机的输入/输出完成中断请求的中断接受（52,62） 检查（54,64），其识别对于运行中的虚拟机的输入/输出完成中断请求的存在并且激活输入/输出完成中断处理;以及通知总线（5），用于发送输入/输出完成中断请求 以及当特定虚拟机被激活时特定虚拟机的标识符到其他指令处理器。 指令处理器的这种中断接受（52,62）还包括用于强制地启动中断检查（54,64）的输入（90）意味着在接收到来自其他指令的输入/输出完成中断和特定虚拟机的标识符 处理器。

    Arrangement and a method for handling interrupt requests in a data processing system in a virtual machine mode
    10.
    发明授权
    Arrangement and a method for handling interrupt requests in a data processing system in a virtual machine mode 失效
    一种在虚拟机模式下处理数据处理系统中的中断请求的方案和方法

    公开(公告)号：US5291605A

    公开(公告)日：1994-03-01

    申请号：US831269

    申请日：1992-02-07

    申请人： Hitoshi Takagi ,  Muneharu Miyazaki

    发明人： Hitoshi Takagi ,  Muneharu Miyazaki

    IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F13/10 ,  G06F13/24 ,  G06F12/08

    CPC分类号： G06F13/24 ,  G06F13/10

    摘要： A technique for handling an interrupt request issued from an I/O (Input/Output) device controller in a data processing system which is operative in a virtual machine mode in which two flags are provided, the first one of which is set to an "on" state in the case where a CPU (Central Processing Unit) is utilized as a master unit and is set to "off" state in the case where the CPU is utilized as a slave unit. The second flag is set to an "on" state in the case where the CPU is utilized as the master unit and is able to accept the interrupt request directed to a guest OS (Operating System). A first logic gate is arranged to issue a logical product of the output of the first flag and one of the outputs of the I/O device controller. A second logic gate is provided to issue a logical product of the output of the second flag and another of the outputs of the I/O device controller. Further, a third logic gate is arranged to issue a logical sum of the outputs of the first and second gates. An interrupt activator is responsive to the output of the third logic gate and then checks to see if the interrupt request issued from the I/O device controller is acceptable.

    摘要翻译： 一种用于处理数据处理系统中的I / O（输入/输出）设备控制器发出的中断请求的技术，该数据处理系统以提供两个标志的虚拟机模式操作，其中第一个设置为“ 在CPU用作主单元的情况下使用CPU（中央处理单元）并且在CPU被用作从单元的情况下被设置为“关闭”状态的情况下为“开”状态。 在CPU用作主单元并且能够接受针对客户OS（操作系统）的中断请求的情况下，第二标志被设置为“接通”状态。 第一逻辑门布置成发出第一标志的输出和I / O设备控制器的输出之一的逻辑积。 提供第二逻辑门以发出第二标志的输出和I / O设备控制器的另一输出的逻辑积。 此外，第三逻辑门布置成发出第一和第二门的输出的逻辑和。 中断激活器响应于第三逻辑门的输出，然后检查以查看从I / O设备控制器发出的中断请求是否可接受。