公开(公告)号：US20060081337A1

公开(公告)日：2006-04-20

申请号：US11292368

申请日：2005-12-02

申请人： Shinji Himori ,  Kimihiro Higuchi ,  Tatsuo Matsudo ,  Etsuo Iijima ,  Hiroharu Ito ,  Shoichiro Matsuyama ,  Noriaki Imai ,  Kazuya Nagaseki

发明人： Shinji Himori ,  Kimihiro Higuchi ,  Tatsuo Matsudo ,  Etsuo Iijima ,  Hiroharu Ito ,  Shoichiro Matsuyama ,  Noriaki Imai ,  Kazuya Nagaseki

IPC分类号： C23F1/00 ,  C23C14/00

CPC分类号： H01J37/32091 ,  H01J2237/2001

摘要： A capacitive coupling plasma processing apparatus includes a process chamber configured to have a vacuum atmosphere, and a process gas supply section configured to supply a process gas into the chamber. In the chamber, a first electrode serving as a cathode electrode, and a second electrode grounded to serve as an anode electrode are disposed opposite each other. An RF power supply is disposed to supply an RF power to the first electrode to form an RF electric field within a plasma generation region between the first and second electrodes, so as to turn the process gas into plasma. The target substrate is supported by a support member between the first and second electrodes such that a process target surface thereof faces the second electrode. The second electrode includes a conductive counter surface facing the first electrode and exposed to the plasma generation region.

摘要翻译： 电容耦合等离子体处理装置包括被配置为具有真空气氛的处理室和被配置为将处理气体供应到室中的处理气体供给部。 在室中，用作阴极的第一电极和接地以用作阳极的第二电极彼此相对地设置。 设置RF电源以向第一电极提供RF功率以在第一和第二电极之间的等离子体产生区域内形成RF电场，以将处理气体转化为等离子体。 目标基板由第一和第二电极之间的支撑构件支撑，使得其工艺目标表面面向第二电极。 第二电极包括面向第一电极并暴露于等离子体产生区域的导电计数器表面。

公开(公告)号：US07531460B2

公开(公告)日：2009-05-12

申请号：US11392506

申请日：2006-03-30

申请人： Etsuo Iijima ,  Meiki Koh

发明人： Etsuo Iijima ,  Meiki Koh

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3065 ,  H01L21/76229 ,  Y10S438/978

摘要： A dry-etching method using an apparatus where a wafer is placed on either of a pair of opposed electrodes provided in an etching chamber, and high-frequency power is supplied to both the opposed electrodes to effect a plasma etching. The plasma etching uses a gas containing at least Cl2 and HBr. Trenches 104a, 104b are formed, as shown in FIG. 1B, in a silicon wafer 101 shown in FIG. 1A through a mask layer such as a nitride silicon layer 103. While adjusting the high-frequency power supplied to the opposed electrode where the wafer is placed, the shape of the sidewalls 105a, 105b of the trenches 104a, 104b is controlled. Thus, the trenches can have desired shapes even if the widths of the trenches are different.

摘要翻译： 使用将晶片放置在设置在蚀刻室中的一对相对电极中的任一个上的设备的干蚀刻方法，并且向相对电极提供高频电力以进行等离子体蚀刻。 等离子体蚀刻使用至少包含Cl 2和HBr的气体。 形成沟槽104a，104b，如图1所示。 如图1B所示，在图1所示的硅晶片101中， 通过诸如氮化物硅层103的掩模层，在调整提供给放置晶片的相对电极的高频功率时，控制沟槽104a，104b的侧壁105a，105b的形状。 因此，即使沟槽的宽度不同，沟槽也可以具有期望的形状。

公开(公告)号：US20090098736A1

公开(公告)日：2009-04-16

申请号：US12335872

申请日：2008-12-16

申请人： Etsuo Iijima ,  Norikazu Yamada

发明人： Etsuo Iijima ,  Norikazu Yamada

IPC分类号： H01L21/3065

CPC分类号： H01J37/32935 ,  H01L21/32137

摘要： A main etching step is effected in a state shown in FIG. 1A under a first pressure using a gas containing at least HBr, e.g., a mixture gas of HBr and Cl2 as an etching gas. The main etching is ended before a silicon oxide film 102, as shown in FIG. 1B, is exposed. An over-etching process is effected under a second pressure higher than the first pressure using a gas containing at least HBr, e.g., an HBr single gas so as to completely expose the silicon oxide film 102 as shown in FIG. 1C. In such a way, the selectivity of a silicon-containing conductive layer with respect to the silicon oxide film is improved compared to conventional methods. Without etching the silicon oxide film layer, which is an underlying layer, and without marring the shape of the silicon-containing conductive film layer formed by etching, only the desired silicon-containing conductive film layer is removed by etching reliably.

摘要翻译： 主蚀刻步骤在图3所示的状态下进行。 在第一压力下使用至少包含HBr的气体，例如作为蚀刻气体的HBr和Cl2的混合气体。 主蚀刻在氧化硅膜102之前结束，如图1所示。 1B ，被暴露。 使用高于第一压力的第二压力，使用至少包含HBr的气体，例如HBr单一气体进行过蚀刻工艺，以便完全暴露氧化硅膜102，如图中所示。 >图。 1C 。 以这种方式，与常规方法相比，含硅导电层相对于氧化硅膜的选择性得到改善。 在不蚀刻作为下层的氧化硅膜层的情况下，不侵蚀通过蚀刻形成的含硅导电膜层的形状，仅通过可靠地蚀刻除去所需的含硅导电膜层。

公开(公告)号：US08288286B2

公开(公告)日：2012-10-16

申请号：US12335872

申请日：2008-12-16

申请人： Etsuo Iijima ,  Norikazu Yamada

发明人： Etsuo Iijima ,  Norikazu Yamada

IPC分类号： H01L21/302

CPC分类号： H01J37/32935 ,  H01L21/32137

摘要： A main etching step is effected in a state shown in FIG. 1A under a first pressure using a gas containing at least HBr, e.g., a mixture gas of HBr and Cl2 as an etching gas. The main etching is ended before a silicon oxide film 102, as shown in FIG. 1B, is exposed. An over-etching process is effected under a second pressure higher than the first pressure using a gas containing at least HBr, e.g., an HBr single gas so as to completely expose the silicon oxide film 102 as shown in FIG. 1C. In such a way, the selectivity of a silicon-containing conductive layer with respect to the silicon oxide film is improved compared to conventional methods. Without etching the silicon oxide film layer, which is an underlying layer, and without marring the shape of the silicon-containing conductive film layer formed by etching, only the desired silicon-containing conductive film layer is removed by etching reliably.

摘要翻译： 在图1所示的状态下进行主蚀刻步骤。 在第一压力下使用至少包含HBr的气体，例如HBr和Cl2的混合气体作为蚀刻气体。 主蚀刻在氧化硅膜102之前结束，如图3所示。 1B，暴露。 在比第一压力高的第二压力下使用至少包含HBr的气体，例如HBr单一气体进行过蚀刻工艺，以便如图1所示完全暴露氧化硅膜102。 1C。 以这种方式，与常规方法相比，含硅导电层相对于氧化硅膜的选择性得到改善。 在不蚀刻作为下层的氧化硅膜层的情况下，不侵蚀通过蚀刻形成的含硅导电膜层的形状，仅通过可靠地蚀刻除去所需的含硅导电膜层。

公开(公告)号：US20060172546A1

公开(公告)日：2006-08-03

申请号：US11392506

申请日：2006-03-30

申请人： Etsuo Iijima ,  Meiki Koh

发明人： Etsuo Iijima ,  Meiki Koh

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3065 ,  H01L21/76229 ,  Y10S438/978

摘要： A dry-etching method using an apparatus where a wafer is placed on either of a pair of opposed electrodes provided in an etching chamber, and high-frequency power is supplied to both the opposed electrodes to effect a plasma etching. The plasma etching uses a gas containing at least Cl2 and HBr. Trenches 104a, 104b are formed, as shown in FIG. 1B, in a silicon wafer 101 shown in FIG. 1A through a mask layer such as a nitride silicon layer 103. While adjusting the high-frequency power supplied to the opposed electrode where the wafer is placed, the shape of the sidewalls 105a, 105b of the trenches 104a, 104b is controlled. Thus, the trenches can have desired shapes even if the widths of the trenches are different.

摘要翻译： 使用将晶片放置在设置在蚀刻室中的一对相对电极中的任一个上的设备的干蚀刻方法，并且向相对电极提供高频电力以进行等离子体蚀刻。 等离子体蚀刻使用至少包含Cl 2 2和HBr的气体。 形成了沟槽104a，104b，如图3所示。 在图13中所示的硅晶片101中，示出了图1B所示的硅晶片101。 通过诸如氮化物硅层103的掩模层，在调整提供给放置晶片的相对电极的高频功率时，沟槽104a的侧壁105a，105b的形状 ，104b被控制。 因此，即使沟槽的宽度不同，沟槽也可以具有期望的形状。

公开(公告)号：US07504040B2

公开(公告)日：2009-03-17

申请号：US11711769

申请日：2007-02-28

申请人： Etsuo Iijima ,  Hiroshi Tsuchiya

发明人： Etsuo Iijima ,  Hiroshi Tsuchiya

IPC分类号： B05D1/04

CPC分类号： H01L21/31116 ,  H01J37/32082 ,  H01J37/32935 ,  H01L21/32137

摘要： An RF power (Bottom RF) from a radio-frequency power source 12 is turned off (t5) and the supply of a He gas 14 to a back face of a wafer W is stopped (t5) when an end point detector 17 (EPD) detects an end point (t5), and a high-voltage DC power source 13 (HV) is turned off (t6) under the condition in which an RF power (Top RF) from a radio-frequency power source 11 is controlled to fall within a range in which etching does not progress and plasma discharge can be maintained (t5). This process enables the inhibition of the adhesion of particles while an etching amount is accurately controlled.

摘要翻译： 来自射频电源12的RF功率（底部RF）被关闭（t5），并且当端点检测器17（EPD）时，停止向晶片W的背面提供He气体14（t5） ）检测终点（t5），并且在将来自射频电源11的RF功率（顶部RF）控制到的条件下，高压DC电源13（HV）被关闭（t6） 落在不进行蚀刻的范围内，能够维持等离子体放电（t5）。 该方法能够在蚀刻量被精确控制的同时抑制颗粒的粘附。

公开(公告)号：US07476624B2

公开(公告)日：2009-01-13

申请号：US10480821

申请日：2002-06-07

申请人： Etsuo Iijima ,  Norikazu Yamada

发明人： Etsuo Iijima ,  Norikazu Yamada

IPC分类号： H01L21/302

CPC分类号： H01J37/32935 ,  H01L21/32137

摘要： A main etching step is effected in a state shown in FIG. 1A under a first pressure using a gas containing at least HBr, e.g., a mixture gas of HBr and Cl2 as an etching gas. The main etching is ended before a silicon oxide film 102, as shown in FIG. 1B, is exposed. An over-etching process is effected under a second pressure higher than the first pressure using a gas containing at least HBr, e.g., an HBr single gas so as to completely expose the silicon oxide film 102 as shown in FIG. 1C. In such a way, the selectivity of a silicon-containing conductive layer with respect to the silicon oxide film is improved compared to conventional methods. Without etching the silicon oxide film layer, which is an underlying layer, and without marring the shape of the silicon-containing conductive film layer formed by etching, only the desired silicon-containing conductive film layer is removed by etching reliably.

摘要翻译： 在图1所示的状态下进行主蚀刻步骤。 在第一压力下使用至少包含HBr的气体，例如HBr和Cl2的混合气体作为蚀刻气体。 主蚀刻在氧化硅膜102之前结束，如图3所示。 1B，暴露。 在比第一压力高的第二压力下使用至少包含HBr的气体，例如HBr单一气体进行过蚀刻工艺，以便如图1所示完全暴露氧化硅膜102。 1C。 以这种方式，与常规方法相比，含硅导电层相对于氧化硅膜的选择性得到改善。 在不蚀刻作为下层的氧化硅膜层的情况下，不侵蚀通过蚀刻形成的含硅导电膜层的形状，仅通过可靠地蚀刻除去所需的含硅导电膜层。

公开(公告)号：US20070148364A1

公开(公告)日：2007-06-28

申请号：US11711769

申请日：2007-02-28

申请人： Etsuo Iijima ,  Hiroshi Tsuchiya

发明人： Etsuo Iijima ,  Hiroshi Tsuchiya

IPC分类号： B05D1/04

CPC分类号： H01L21/31116 ,  H01J37/32082 ,  H01J37/32935 ,  H01L21/32137

摘要： An RF power (Bottom RF) from a radio-frequency power source 12 is turned off (t5) and the supply of a He gas 14 to a back face of a wafer W is stopped (t5) when an end point detector 17 (EPD) detects an end point (t5), and a high-voltage DC power source 13 (HV) is turned off (t6) under the condition in which an RF power (Top RF) from a radio-frequency power source 11 is controlled to fall within a range in which etching does not progress and plasma discharge can be maintained (t5). This process enables the inhibition of the adhesion of particles while an etching amount is accurately controlled.

摘要翻译： 关闭来自射频电源12的RF功率（底部RF）（t 5），并且当端点检测器17（t 5）停止向晶片W的背面提供He气体14时（t 5） （EPD）检测终点（t 5），并且在来自射频电源的RF功率（Top RF）的条件下，高压DC电源13（HV）截止（t 6） 11被控制在不进行蚀刻的范围内，能够维持等离子体放电（t 5）。 该方法能够在蚀刻量被精确控制的同时抑制颗粒的粘附。

公开(公告)号：US07183217B2

公开(公告)日：2007-02-27

申请号：US10481645

申请日：2002-06-07

申请人： Etsuo Iijima ,  Akiteru Koh

发明人： Etsuo Iijima ,  Akiteru Koh

IPC分类号： H01L21/311

CPC分类号： H01L21/3065 ,  H01L21/76229 ,  Y10S438/978

摘要： A dry-etching method using an apparatus where a wafer is placed on either of a pair of opposed electrodes provided in an etching chamber, and high-frequency power is supplied to both the opposed electrodes to effect a plasma etching. The plasma etching uses a gas containing at least Cl2 and HBr. Trenches 104a, 104b are formed, as shown in FIG. 1B, in a silicon wafer 101 shown in FIG. 1A through a mask layer such as a nitride silicon layer 103. While adjusting the high-frequency power supplied to the opposed electrode where the wafer is placed, the shape of the sidewalls 105a, 105b of the trenches 104a, 104b is controlled. Thus, the trenches can have desired shapes even if the widths of the trenches are different.

摘要翻译： 使用将晶片放置在设置在蚀刻室中的一对相对电极中的任一个上的设备的干蚀刻方法，并且向相对电极提供高频电力以进行等离子体蚀刻。 等离子体蚀刻使用至少包含Cl 2 2和HBr的气体。 形成沟槽104a，104b，如图1所示。 如图1B所示，在图1所示的硅晶片101中， 如图1A所示，通过诸如氮化物硅层103的掩模层。 在调整提供给放置晶片的相对电极的高频功率的同时，控制沟槽104a，104b的侧壁105a，105b的形状。 因此，即使沟槽的宽度不同，沟槽也可以具有期望的形状。