摘要:
A pipelined processor is provided with a plurality of control stages controlling a datapath made up of a plurality of parallel static-type data latches. The latches each include a feedback circuit, typically a field-effect transistor, which is enabled by a data latch control signal from a particular control stage. Enabling the feedback stage consumes power. A data stagnation detection circuit detects a data stagnation in the datapath, by use of handshake control signals exchanged between the control stages. The data stagnation detection circuit inhibits enablement of the feedback circuit when no data stagnation is detected, reducing power used in the latch.
摘要:
In a data flow machine, a program stored in advance is read out based on a tag included in a packet when the packet including first data is inputted from an external portion. Then, an instruction packet is formed by the content read out as a new tag and the first data, so that the instruction packet is outputted. Second data including the same tag as that included in the first data of the instruction packet read out from the program memory is detected. Firing processing is performed with respect to the first data and the second data as a pair and arithmetic processing is performed according to the instruction as a part of the tag included in an arithmetic packet, so that the arithmetic packet is outputted as a packet. The tag included in the packet is determined and the packet is outputted to an external portion or is inputted again to the internal portion.
摘要:
In a data driven type information processing apparatus, an operation processing unit. The operation processing unit executes processing of a high function instruction on the basis of corresponding information stored in a specification data memory, and branches data packets, received from a pair data detecting unit, to a simple instruction processing unit. The apparatus further includes a junction unit for joining data packets outputted from the high function and the simple function instruction processing units to output them to an output unit.
摘要:
A data-driven type computer system including an input limiting section for monitoring a current number of packets existing in the circular pipeline of the system while being processed. The input limiting section is adapted to control packets from being inputted from the external unit when the current number of packets exceeds a specified threshold value which is greater than a minimum packet number existing in the circular pipeline and which allows the attainment of the highest possible throughput of the system. The input limiting section further includes a predictive control unit to preliminarily analyze a current data flow graph to be processed in the system and also to take order in rank a possible rate of increase in the quantity of packets generated by a copying operation as well as a possible rate of reduction in the prior processing by the system. While being stored once for buffering by an input buffer, variation in the current quantity of deposited packets is predicted by the predictive control unit every time when packets are entered from an external source or from the output section, so that they are prevented from being entered by the input limiting section when the current quantity of deposited packets is in excess of the preset limit of the hardware.
摘要:
A parallel processor developing system comprises a control computer, an interface portion, a processing element, a tracer portion and a display portion. The processing element comprises a data driven type processor. The interface portion stores data packets supplied from the control computer and applies the data packets to the processing element at a predetermined time interval. The tracer portion stores the data packets supplied from predetermined ports of the processing element together with time information. The display portion displays storage contents of the tracer portion.
摘要:
A tag data processing apparatus is described for use in a data flow computer utilizing a tagged token scheme. A tag adding process and tag restoring process are executed by using pipeline registers, a queue memory and simple control circuit, thereby obtaining high speed operation and superior throughput without the need for a tag memory table, complicated operation-test circuitry or a sequence control circuit.
摘要:
A coincidence element responsive to a plurality of input signals for outputting the level of the input signals when said plurality of input signals coincide with each other includes, a serial connection of a first electrically conductive type and a second electrically conductive type MOS transistors of the same number, the number being equal to the number of the input signals, responsive to said plurality of inputs connected between a first power supply and a second power supply; and a CMOS inverter responsive to an intermediate output at the connection of the most lower stage first conductivity type MOS transistor and the most upper stage second conductivity type MOS transistor for outputting a coincidence signal.
摘要:
In a data transmission apparatus, a plurality of data processing modules are used and required sequence setting is performed to a port sequencer of input/output ports of each data processing module, and the daisy chain transfer of the selective data transfer, the load distribution data transfer, the collective data transfer is combined between the data processing modules, thereby the data transmission is performed efficiently at high speed.
摘要:
In a data transmission apparatus, a plurality of data processing modules are used and required sequence setting is performed to a port sequencer of input/output ports of each data processing module. The daisy chain transfer of the selective data transfer, the load distribution data transfer, the collective data transfer is combined between the data processing modules, thereby the data transmission is performed efficiently at high speed.