公开(公告)号：US20060057796A1

公开(公告)日：2006-03-16

申请号：US10531582

申请日：2003-10-03

申请人： Shinsuke Harada ,  Tsutomu Yatsuo ,  Kenji Fukuda ,  Mitsuo Okamoto ,  Kazuhiro Adachi

发明人： Shinsuke Harada ,  Tsutomu Yatsuo ,  Kenji Fukuda ,  Mitsuo Okamoto ,  Kazuhiro Adachi

IPC分类号： H01L21/8238

CPC分类号： H01L29/66477 ,  H01L21/02529 ,  H01L21/0465 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7802

摘要： A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.

摘要翻译： 具有低导通电阻和高阻断电压的碳化硅垂直MOSFET。 在第一导电类型的高浓度碳化硅衬底的表面上形成第一导电类型的低浓度碳化硅的第一沉积膜。 形成在第一沉积膜上的是第二沉积膜，其包括第二导电类型的高浓度栅极区域，其中第一区域被选择性地去除。 在第二沉积膜上形成第三沉积膜，其包括比选择性去除的第一区域宽的第二区域，第一导电类型的高浓度源区域和第二导电类型的低浓度栅极区域。 第一导电类型的低浓度基区形成为与第一和第二区域中的第一沉积膜接触。

公开(公告)号：US08952391B2

公开(公告)日：2015-02-10

申请号：US10531582

申请日：2003-10-03

申请人： Shinsuke Harada ,  Tsutomu Yatsuo ,  Kenji Fukuda ,  Mitsuo Okamoto ,  Kazuhiro Adachi ,  Seiji Suzuki

发明人： Shinsuke Harada ,  Tsutomu Yatsuo ,  Kenji Fukuda ,  Mitsuo Okamoto ,  Kazuhiro Adachi ,  Seiji Suzuki

IPC分类号： H01L29/15 ,  H01L29/66 ,  H01L21/04 ,  H01L29/78 ,  H01L21/02 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423

CPC分类号： H01L29/66477 ,  H01L21/02529 ,  H01L21/0465 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7802

摘要： A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.

摘要翻译： 具有低导通电阻和高阻断电压的碳化硅垂直MOSFET。 在第一导电类型的高浓度碳化硅衬底的表面上形成第一导电类型的低浓度碳化硅的第一沉积膜。 形成在第一沉积膜上的是第二沉积膜，其包括第二导电类型的高浓度栅极区域，其中第一区域被选择性地去除。 在第二沉积膜上形成第三沉积膜，其包括比选择性去除的第一区域宽的第二区域，第一导电类型的高浓度源区域和第二导电类型的低浓度栅极区域。 第一导电类型的低浓度基区形成为与第一和第二区域中的第一沉积膜接触。

公开(公告)号：US20100012951A1

公开(公告)日：2010-01-21

申请号：US12310992

申请日：2007-09-13

申请人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Mitsuo Okamoto ,  Kenji Fukuda ,  Makoto Kato

发明人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Mitsuo Okamoto ,  Kenji Fukuda ,  Makoto Kato

IPC分类号： H01L29/24 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L21/046 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

摘要： In an SiC vertical MOSFET comprising a channel region and an n-type inverted electron guide path formed through ion implantation in a low-concentration p-type deposition film, the width of the channel region may be partly narrowed owing to implantation mask positioning failure, and the withstand voltage of the device may lower, and therefore, the device could hardly satisfy both low on-resistance and high withstand voltage. In the invention, second inverted layers (41, 42) are provided at the same distance on the right and left sides from the inverted layer (40) to be the electron guide path in the device, and the inverted layers are formed through simultaneous ion implantation using the same mask, and accordingly, the length of all the channel regions in the device is made uniform, thereby solving the problem.

公开(公告)号：US20090173949A1

公开(公告)日：2009-07-09

申请号：US12281391

申请日：2006-12-27

申请人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Kenji Fukuda ,  Mitsuo Okamoto

发明人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Kenji Fukuda ,  Mitsuo Okamoto

IPC分类号： H01L29/24 ,  H01L21/336

CPC分类号： H01L21/8213 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7806

摘要： This invention has a cell incorporating a built-in Schottky diode region disposed in at least part of an elementary cell that constitutes an SiC vertical MOSFET provided in a low-density p-type deposit film with a channel region and a base region inverted to an n-type by ion implantation. This built-in Schottky diode region has built therein a Schottky diode of low on-resistance that is formed of a second deficient pan disposed in a high-density gate layer, a second n-type base layer penetrating a low-density p-type deposit layer formed thereon, reaching an n-type drift layer of the second deficient part and attaining its own formation in consequence of inversion of the p-type deposit layer into an n-type by the ion implantation of an n-type impurity from the surface, and a source electrode connected in the manner of forming a Schottky barrier to the surface-exposed part of the second n-type base layer.

摘要翻译： 本发明具有一个电池，该电池结合了内置的肖特基二极管区域，该区域设置在构成在具有沟道区域和基极区域的低密度p型沉积膜中提供的SiC垂直MOSFET的基本单元的至少一部分中 n型离子注入。 该内置的肖特基二极管区域内置有低导通电阻的肖特基二极管，该二极管由设置在高密度栅极层中的第二缺陷盘形成，第二n型基极层穿透低密度p型 沉积层形成在其上，到达第二缺陷部分的n型漂移层，并且由于p型沉积层通过从n型杂质离子注入n型杂质而转变为n型，从而形成其自身的形成 表面以及以与第二n型基底层的表面暴露部分形成肖特基势垒的方式连接的源电极。

公开(公告)号：US20080203400A1

公开(公告)日：2008-08-28

申请号：US12025445

申请日：2008-02-04

申请人： Kenji Fukuda ,  Junji Senzaki ,  Shinsuke Harada ,  Makoto Kato ,  Tsutomu Yatsuo ,  Mitsuo Okamoto

发明人： Kenji Fukuda ,  Junji Senzaki ,  Shinsuke Harada ,  Makoto Kato ,  Tsutomu Yatsuo ,  Mitsuo Okamoto

IPC分类号： H01L29/161

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L21/8213 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7835

摘要： A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.

摘要翻译： 提供半导体器件和使用（000-1）面的碳化硅衬底的器件的制造方法。 通过优化栅极氧化后使用的热处理方法来制造具有高阻断电压和高沟道迁移率的SiC半导体器件。 制造半导体器件的方法包括以下步骤：在由具有（000-1）面取向的碳化硅形成的半导体区上形成栅极绝缘层，在栅极绝缘层上形成栅电极，在半导体上形成电极 区域，清洁半导体区域表面。 在800℃至1150℃的温度下，在含有1％或更多的H 2 O（水）蒸气的气氛中形成栅极绝缘层，以降低界面陷阱密度 栅极绝缘层和半导体区域之间的界面。

公开(公告)号：US08003991B2

公开(公告)日：2011-08-23

申请号：US12281391

申请日：2006-12-27

申请人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Kenji Fukuda ,  Mitsuo Okamoto

发明人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Kenji Fukuda ,  Mitsuo Okamoto

IPC分类号： H01L29/15

CPC分类号： H01L21/8213 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7806

摘要： This invention has a cell incorporating a built-in Schottky diode region disposed in at least part of an elementary cell that constitutes an SiC vertical MOSFET provided in a low-density p-type deposit film with a channel region and a base region inverted to an n-type by ion implantation. This built-in Schottky diode region has built therein a Schottky diode of low on-resistance that is formed of a second deficient pan disposed in a high-density gate layer, a second n-type base layer penetrating a low-density p-type deposit layer formed thereon, reaching an n-type drift layer of the second deficient part and attaining its own formation in consequence of inversion of the p-type deposit layer into an n-type by the ion implantation of an n-type impurity from the surface, and a source electrode connected in the manner of forming a Schottky barrier to the surface-exposed part of the second n-type base layer.

摘要翻译： 本发明具有一个电池，该电池结合了内置的肖特基二极管区域，该区域设置在构成在具有沟道区域和基极区域的低密度p型沉积膜中提供的SiC垂直MOSFET的基本单元的至少一部分中 n型离子注入。 该内置的肖特基二极管区域内置有低导通电阻的肖特基二极管，该二极管由设置在高密度栅极层中的第二缺陷盘形成，第二n型基极层穿透低密度p型 沉积层形成在其上，到达第二缺陷部分的n型漂移层，并且由于p型沉积层通过从n型杂质离子注入n型杂质而转变为n型，从而形成其自身的形成 表面以及以与第二n型基底层的表面暴露部分形成肖特基势垒的方式连接的源电极。

公开(公告)号：US07880173B2

公开(公告)日：2011-02-01

申请号：US12025445

申请日：2008-02-04

申请人： Kenji Fukuda ,  Junji Senzaki ,  Shinsuke Harada ,  Makoto Kato ,  Tsutomu Yatsuo ,  Mitsuo Okamoto

发明人： Kenji Fukuda ,  Junji Senzaki ,  Shinsuke Harada ,  Makoto Kato ,  Tsutomu Yatsuo ,  Mitsuo Okamoto

IPC分类号： H01L29/15

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L21/8213 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7835

摘要： A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.

摘要翻译： 提供半导体器件和使用（000-1）面的碳化硅衬底的器件的制造方法。 通过优化栅极氧化后使用的热处理方法来制造具有高阻断电压和高沟道迁移率的SiC半导体器件。 制造半导体器件的方法包括以下步骤：在由具有（000-1）面取向的碳化硅形成的半导体区上形成栅极绝缘层，在栅极绝缘层上形成栅电极，在半导体上形成电极 区域，清洁半导体区域表面。 栅极绝缘层在800℃至1150℃的温度下在含有1％或更多的H 2 O（水）蒸汽的气氛中形成，以降低栅绝缘层和半导体之间的界面的界面陷阱密度 地区。

公开(公告)号：US07728336B2

公开(公告)日：2010-06-01

申请号：US12310992

申请日：2007-09-13

申请人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Mitsuo Okamoto ,  Kenji Fukuda ,  Makoto Kato

发明人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Mitsuo Okamoto ,  Kenji Fukuda ,  Makoto Kato

IPC分类号： H01L31/0312

CPC分类号： H01L29/7802 ,  H01L21/046 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

摘要： In an SiC vertical MOSFET comprising a channel region and an n-type inverted electron guide path formed through ion implantation in a low-concentration p-type deposition film, the width of the channel region may be partly narrowed owing to implantation mask positioning failure, and the withstand voltage of the device may lower, and therefore, the device could hardly satisfy both low on-resistance and high withstand voltage. In the invention, second inverted layers (41, 42) are provided at the same distance on the right and left sides from the inverted layer (40) to be the electron guide path in the device, and the inverted layers are formed through simultaneous ion implantation using the same mask, and accordingly, the length of all the channel regions in the device is made uniform, thereby solving the problem.

摘要翻译： 在包括在低浓度p型沉积膜中通过离子注入形成的沟道区和n型反向电子引导路径的SiC垂直MOSFET中，由于注入掩模定位失败，沟道区的宽度可能部分变窄， 并且器件的耐压可能降低，因此器件几乎不能满足低导通电阻和高耐压两者。 在本发明中，第二倒置层（41,42）从反转层（40）的左右两侧设置为相同距离，作为装置中的电子引导路径，反相层通过同时离子 使用相同的掩模进行注入，因此，将器件中的所有沟道区域的长度均匀化，从而解决问题。

公开(公告)号：US20090134402A1

公开(公告)日：2009-05-28

申请号：US11718036

申请日：2005-09-30

申请人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Mitsuo Okamoto ,  Kenji Fukuda

发明人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Mitsuo Okamoto ,  Kenji Fukuda

IPC分类号： H01L29/78 ,  H01L21/3205 ,  H01L21/02

CPC分类号： H01L29/7802 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7828

摘要： In the SiC vertical MOSFET having a low-concentration p-type deposition film provided therein with a channel region and a base region resulting from reverse-implantation to n-type through ion implantation, dielectric breakdown of gate oxide film used to occur at the time of off, thereby preventing a further blocking voltage enhancement. This problem has been resolved by interposing of a low-concentration n-type deposition film between a low-concentration p-type deposition film and a high-concentration gate layer and selectively forming of a base region resulting from reverse-implantation to n-type through ion implantation in the low-concentration p-type deposition film so that the thickness of deposition film between the high-concentration gate layer and each of channel region and gate oxide layer is increased.

摘要翻译： 在具有在其中设置有沟道区域的低浓度p型沉积膜和由n型通过离子注入的反向注入产生的基极区域的SiC垂直MOSFET中，用于当时发生的栅极氧化膜的介电击穿 关闭，从而防止进一步的阻塞电压增强。 通过在低浓度p型沉积膜和高浓度栅极层之间插入低浓度n型沉积膜并且将由反向注入产生的碱性区域选择性地形成为n型，已经解决了该问题 通过离子注入低浓度p型沉积膜，使得高浓度栅极层与沟道区域和栅极氧化物层之间的沉积膜的厚度增加。

公开(公告)号：US20090072244A1

公开(公告)日：2009-03-19

申请号：US12281902

申请日：2007-01-16

申请人： Shinsuke Harada ,  Makoto Katou ,  Kenji Fukuda ,  Tsutomu Yatsuo

发明人： Shinsuke Harada ,  Makoto Katou ,  Kenji Fukuda ,  Tsutomu Yatsuo

IPC分类号： H01L29/24 ,  H01L21/44

CPC分类号： H01L21/31658 ,  H01L21/02126 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02337 ,  H01L21/046 ,  H01L21/0485 ,  H01L21/324 ,  Y10S438/931

摘要： The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen.

摘要翻译： 本发明的目的是提供一种用于制造半导体器件的方法，该半导体器件为了形成这种欧姆接触的目的而进行了退火处理，以能够降低欧姆接触电阻并且提供在碳化硅的（000-1）面上， 绝缘膜并提供半导体器件。 制造碳化硅半导体器件的方法包括以下步骤：在至少包含氧和水分的气体中在碳化硅半导体的（000-1）面上进行热氧化，从而以这种方式形成绝缘膜 为了接触碳化硅半导体的（000-1）面，除去绝缘膜的一部分，从而在其中形成开口部，在开口部的至少一部分上沉积接触金属，进行热处理，从而形成 接触金属和碳化硅的反应层，其中热处理在惰性气体和氢气的混合气体中实施。