公开(公告)号：US5355331A

公开(公告)日：1994-10-11

申请号：US185169

申请日：1994-01-24

申请人： Shinsuke Takase ,  Toshiya Kato

发明人： Shinsuke Takase ,  Toshiya Kato

IPC分类号： G11C11/41 ,  G11C5/14 ,  G11C11/413 ,  G11C11/417 ,  G11C29/02 ,  H01L21/66 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C11/417

摘要： According to this invention, there is disclosed a semiconductor device in which a memory section and a logic section are arranged on the same semiconductor chip, comprising a high-resistance element constituting a memory cell, a low-resistance line connected to the high-resistance element, a power source line serving as a power source path from a power source pad, a switching element arranged between the low-resistance line and the power source line, and a control circuit for controlling the switching element.

摘要翻译： 根据本发明，公开了一种半导体器件，其中存储部分和逻辑部分布置在相同的半导体芯片上，包括构成存储单元的高电阻元件，连接到高电阻的低电阻线 元件，作为来自电源焊盘的电源路径的电源线，布置在低电阻线和电源线之间的开关元件，以及用于控制开关元件的控制电路。

公开(公告)号：US5294837A

公开(公告)日：1994-03-15

申请号：US978046

申请日：1992-11-18

申请人： Shinsuke Takase ,  Hisashi Hashimoto

发明人： Shinsuke Takase ,  Hisashi Hashimoto

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/82 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528 ,  H01L29/92 ,  H01L23/48 ,  H01L29/44

CPC分类号： H01L23/5223 ,  H01L23/528 ,  H01L28/82 ,  H01L2924/0002

摘要： A plurality of standard cells are placed on a semiconductor substrate. A first aluminum wiring layer is connected to those standard cells. Below the first aluminum wiring layer, a second wiring layer is formed which is not connected to the standard cells and which, together with the first wiring layer, forms a capacitor. Between the first and second aluminum wiring layers, an insulating layer is formed. Wiring skew is adjusted by making through-holes in the insulating layer, and connecting the first and second aluminum wiring layers to each other via as many through-holes as required to vary the capacitance between them.

摘要翻译： 多个标准单元被放置在半导体衬底上。 第一铝布线层连接到这些标准单元。 在第一铝布线层下方形成第二布线层，其不连接到标准单元，并且与第一布线层一起形成电容器。 在第一和第二铝布线层之间形成绝缘层。 通过在绝缘层中形成通孔来调节布线偏斜，并且通过所需的多个通孔将第一和第二铝布线层彼此连接以改变它们之间的电容。

公开(公告)号：US5698872A

公开(公告)日：1997-12-16

申请号：US476905

申请日：1995-06-07

申请人： Shinsuke Takase ,  Hisashi Hashimoto ,  Yutaka Tanaka

发明人： Shinsuke Takase ,  Hisashi Hashimoto ,  Yutaka Tanaka

IPC分类号： G11C17/12 ,  H01L21/82 ,  H01L27/10 ,  H01L27/112 ,  H01L27/118 ,  H01L27/040 ,  H01L27/020

CPC分类号： H01L27/112 ,  H01L27/11803 ,  Y10S257/903

摘要： Memory cells, which serve as basic cells, are arranged in a matrix pattern. The memory cells are each provided with a word line which is integral with the gate electrode of a switch element and which is formed of polysilicon. A metallic interconnection layer is arranged above the word line and is applied with substantially the same potential as the word line. The metallic interconnection layer and the word line are connected together via through-holes. The through-holes are formed in through-hole cells, which also serve as basic cells. The through-hole cells and the memory cells are arranged such that the number of rows of the former and the number of rows of the latter are in the ratio of one to at least two.

摘要翻译： 用作基本单元格的存储单元以矩阵模式排列。 存储单元各自设置有与开关元件的栅极整体并且由多晶硅形成的字线。 金属互连层布置在字线上方，并施加与字线大致相同的电位。 金属互连层和字线通过通孔连接在一起。 通孔形成在通孔电池中，其也用作碱性电池。 通孔单元和存储单元被布置成使得前者的行数和后者的行数之比为1至至少2。

公开(公告)号：US5311464A

公开(公告)日：1994-05-10

申请号：US707915

申请日：1991-05-30

申请人： Shinsuke Takase ,  Yutaka Tanaka

发明人： Shinsuke Takase ,  Yutaka Tanaka

IPC分类号： G11C7/00 ,  G11C7/20 ,  G11C11/41 ,  G11C11/412 ,  G11C17/12 ,  H01L21/8244 ,  H01L21/8246 ,  H01L27/11 ,  H01L27/112 ,  G11C11/40

CPC分类号： G11C7/20 ,  G11C11/412 ,  G11C17/12

摘要： The present invention relates to a semiconductor memory cell. The memory cell comprises a word line, a pair of bit lines crossing the word line, a resistance having a first side connected to a high power source and a second side connected to a first connecting node, a first FET connected between the first connecting node and a low power source and having a gate connected to a second connecting node, a second FET connected between the second connecting node and the low power source and having a gate connected to the first connecting node, a third FET connected between the first connecting node and one of the pair of bit lines and having a gate connected to the word line to control the operation of the third FET by changing the potential of the word line, and a fourth FET connected between the second connecting node and the other of the pair of bit lines and having a gate connected to the word line to control the operation of the fourth FET by changing the potential of the word line.

摘要翻译： 本发明涉及半导体存储单元。 存储单元包括字线，与字线交叉的一对位线，具有连接到高功率源的第一侧的电阻和连接到第一连接节点的第二侧，连接在第一连接节点之间的第一FET 和低功率源，并且具有连接到第二连接节点的栅极，连接在第二连接节点和低功率源之间并具有连接到第一连接节点的栅极的第二FET，连接在第一连接节点 并且一对位线中的一个并且具有连接到字线的栅极以通过改变字线的电位来控制第三FET的操作，以及连接在第二连接节点和另一个之间的另一个的第四FET 的位线，并且具有连接到字线的栅极以通过改变字线的电位来控制第四FET的操作。