公开(公告)号：US20130182559A1

公开(公告)日：2013-07-18

申请号：US13553631

申请日：2012-07-19

申请人： Shinya Fujioka ,  Yoshihiro Ashi ,  Masahiko Mizutani ,  Hideki Endo

发明人： Shinya Fujioka ,  Yoshihiro Ashi ,  Masahiko Mizutani ,  Hideki Endo

IPC分类号： H04L12/24

CPC分类号： H04L41/0668 ,  H04L43/0817

摘要： A transmission network is comprised of a network management system for collectively managing and controlling a plurality of transmission devices coupled mutually through transmission routes and the transmission network as well. The network management system includes a plane management table adapted to manage transmission planes defined as a set of paths in the transmission network, and the plane management table has the function to set and manage a transmission plane (working plane) applied during normal operation and besides, a single or a plurality of transmission planes (protection planes) applicable in the event of occurrence of a fault in the transmission network. Then, when a fault occurs in the transmission network, the network management system changes the applied plane to a suitable transmission plane.

公开(公告)号：US08667058B2

公开(公告)日：2014-03-04

申请号：US13527311

申请日：2012-06-19

申请人： Shinya Fujioka ,  Yoshihiro Ashi ,  Masahiko Mizutani

发明人： Shinya Fujioka ,  Yoshihiro Ashi ,  Masahiko Mizutani

IPC分类号： G06F15/16

CPC分类号： H04L67/1095 ,  H04L67/26 ,  H04L67/325 ,  H04L69/28

摘要： When data is disclosed to a plurality of users by using a transfer network and a transfer apparatus, data disclosure time control which cannot be adversely affected by the users is performed to reduce the difference in data disclosure time among the users. A transfer network system includes a distribution server serving as a data-distribution-source transfer apparatus, and a network terminal connected to distribution-destination user equipment. The distribution server and the network terminal each have a time keeping function and a time synchronization function for matching the time of the time keeping function with a master clock. The distribution server sends in advance disclosure data and disclosure time to the network terminal. When the time of the time keeping function of the network terminal matches the disclosure time, the network terminal sends the disclosure data to the user equipment.

摘要翻译： 当通过使用传送网络和传送装置向多个用户公开数据时，执行不受用户不利影响的数据公开时间控制，以减少用户之间的数据公开时间的差异。 传送网络系统包括用作数据分发源传送装置的分发服务器和连接到分发目的地用户设备的网络终端。 分发服务器和网络终端均具有时间保持功能和时间同步功能，用于将时间保持功能的时间与主时钟相匹配。 分发服务器预先向网络终端发送披露数据和公开时间。 当网络终端的时间保持功能与公布时间匹配时，网络终端向用户设备发送公开数据。

公开(公告)号：US20120087662A1

公开(公告)日：2012-04-12

申请号：US13240634

申请日：2011-09-22

申请人： Katsuyoshi Suzuki ,  Masao Niibe ,  Shinya Fujioka ,  Masahiko Mizutani

发明人： Katsuyoshi Suzuki ,  Masao Niibe ,  Shinya Fujioka ,  Masahiko Mizutani

IPC分类号： H04J14/00

CPC分类号： H04J14/0282 ,  H04J3/1694 ,  H04J14/0247 ,  H04J14/0252 ,  H04J14/0256 ,  H04J14/026 ,  H04Q11/0067 ,  H04Q2011/0079

摘要： The OLT manages information of optical intensity and communication bit rate receivable by each ONU, and transmits a signal at suitable optical intensity and a bit rate. The OLT decides a signal transmission plan for each ONU according to a status of accumulated information waiting to be transmitted in the OLT's own device buffer, and inserts the signal transmission plan in a header or payload of a downlink frame, thereby notifying the ONUs of the information prior to transmitting accumulated information (primary signal). The ONU recognizes the signal transmission plan of the OLT according to the time information in a downlink intensity map, receives only a signal having the optical intensity and bit rate suitable for the ONU's own device, and blocks other signals.

摘要翻译： OLT管理每个ONU可接收的光强度和通信比特率信息，并以适当的光强度和比特率发送信号。 OLT根据等待在OLT自己的设备缓冲区中发送的累计信息的状态，决定每个ONU的信号传输计划，并将信号传输计划插入到下行链路帧的报头或有效载荷中，从而通知ONU的 发送累积信息之前的信息（主信号）。 ONU根据下行链路强度图中的时间信息识别OLT的信号传输计划，仅接收具有适合于ONU本身设备的光强度和比特率的信号，并阻止其他信号。

公开(公告)号：US08391715B2

公开(公告)日：2013-03-05

申请号：US13072112

申请日：2011-03-25

申请人： Masao Niibe ,  Masahiko Mizutani ,  Shinya Fujioka

发明人： Masao Niibe ,  Masahiko Mizutani ,  Shinya Fujioka

IPC分类号： H04J14/00 ,  H04B10/04

CPC分类号： H04B10/0793

摘要： When a neighbor ONU receives a signal with light intensity high enough to secure communication between an OLT and a remote ONU, the light intensity may be excessively high to damage a receiver of the neighbor ONU. In order to avoid such a problem, each ONU is notified of a downstream signal transmission plan (downstream light intensity map) prior to transmission of a downstream signal. Each ONU receives the downstream light intensity map (light intensity transmission schedule of downstream signal) in advance. Thus, the neighbor ONU can block or attenuate an optical signal addressed to the remote ONU, and the remote ONU can determine normal operation even when the remote ONU cannot receive a signal addressed to the neighbor ONU. Thus, the remote ONU can be prevented from issuing a wrong error signal.

摘要翻译： 当邻居ONU接收到具有足够高的光强度以保证OLT和远程ONU之间的通信的信号时，光强度可能过高而损坏相邻ONU的接收机。 为了避免这样的问题，在发送下行信号之前，向各ONU通知下行信号发送规划（下行光强度图）。 每个ONU预先接收下游光强度图（下游信号的光强度传输调度）。 因此，邻居ONU可以阻塞或衰减寻址到远程ONU的光信号，并且即使当远程ONU不能接收到寻址到相邻ONU的信号时，远程ONU也可以确定正常操作。 因此，可以防止远程ONU发出错误的错误信号。

公开(公告)号：US07903487B2

公开(公告)日：2011-03-08

申请号：US12201922

申请日：2008-08-29

申请人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

发明人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。

公开(公告)号：US07869296B2

公开(公告)日：2011-01-11

申请号：US11515852

申请日：2006-09-06

申请人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

发明人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

公开(公告)号：US07848176B2

公开(公告)日：2010-12-07

申请号：US12428828

申请日：2009-04-23

申请人： Hitoshi Ikeda ,  Shinya Fujioka ,  Takahiro Sawamura

发明人： Hitoshi Ikeda ,  Shinya Fujioka ,  Takahiro Sawamura

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C7/1018 ,  G11C7/1042 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4085

摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.

摘要翻译： 字控制电路在连续模式下重叠地起动对应于起始行地址和下一行地址的字线。 因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。 可以按顺序的方式访问连接到不同字线的存储单元。 也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。 这可以防止数据传输速率降低。 此外，不需要形成信号和控制电路，用于通知控制器正在切换字线的事实，使得可以简化控制器的半导体存储器件和控制电路的结构。 这导致系统成本的降低。

公开(公告)号：US07778099B2

公开(公告)日：2010-08-17

申请号：US12258970

申请日：2008-10-27

申请人： Shinya Fujioka

发明人： Shinya Fujioka

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615

摘要： A semiconductor memory is provided, the semiconductor memory including a memory core that includes a plurality of memory cells, a refresh generation unit that generates a refresh request for refreshing the memory cell, a core control unit that performs an access operation in response to an access request, a latency determination unit that activates a latency extension signal upon a conflict between activation of a chip enable signal and the refresh request and that deactivates the latency extension signal in response to deactivation of the chip enable signal, a latency output buffer that outputs the latency extension signal, and a data control unit that changes a latency from the access request to a transfer of data to a data terminal during the activation of the latency extension signal.

摘要翻译： 提供了一种半导体存储器，所述半导体存储器包括包括多个存储单元的存储器核心，产生用于刷新存储单元的刷新请求的刷新生成单元，响应于访问执行访问操作的核心控制单元 请求，等待时间确定单元，其在激活芯片使能信号和刷新请求之间的冲突时激活延迟扩展信号，并且响应于芯片使能信号的去激活而停用延迟扩展信号;等待时间输出缓冲器，其输出 延迟扩展信号，以及数据控制单元，其在等待时间延长信号的激活期间将等待时间从访问请求改变为数据传输到数据终端。

公开(公告)号：US07730232B2

公开(公告)日：2010-06-01

申请号：US11113181

申请日：2005-04-25

申请人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

发明人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

IPC分类号： G06F13/00

CPC分类号： G06F12/0804 ,  G06F2212/2022 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C16/06 ,  G11C16/3454

摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.

摘要翻译： 提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。 传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从 响应于确认完成数据传送的传送状态。

公开(公告)号：US07200059B2

公开(公告)日：2007-04-03

申请号：US11260486

申请日：2005-10-28

申请人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

发明人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

IPC分类号： G11C29/00

CPC分类号： G11C29/06 ,  G11C29/10 ,  G11C2029/0405 ,  G11C2029/1204 ,  G11C2029/3602

摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。