公开(公告)号：US5754061A

公开(公告)日：1998-05-19

申请号：US718015

申请日：1996-09-03

申请人： Shinzou Satou ,  Kou Ebihara ,  Akiyoshi Suzuki ,  Keisuke Ishiwata ,  Kouji Miki ,  Hitoshi Ohmichi ,  Tamio Miyamura ,  Masamichi Kamiyama

发明人： Shinzou Satou ,  Kou Ebihara ,  Akiyoshi Suzuki ,  Keisuke Ishiwata ,  Kouji Miki ,  Hitoshi Ohmichi ,  Tamio Miyamura ,  Masamichi Kamiyama

IPC分类号： H03K19/08 ,  H03K19/00 ,  H03K19/003 ,  H03K19/013 ,  H03K19/02 ,  H03K17/04

CPC分类号： H03K19/00353 ,  H03K19/001 ,  H03K19/0136

摘要： A Bi-CMOS circuit includes a first bipolar, a second bipolar transistor and a CMOS control unit for performing switching controls of the first and second bipolar transistors on the basis of an input signal applied to an input terminal and for controlling an output signal output via the output terminal on the basis of the input signal. A turn-OFF unit temporality couples the base of the first bipolar transistor to a low-potential side power supply line on the basis of a current flowing in said control means when the first bipolar transistor is turned OFF, so that the first bipolar transistor can be rapidly turned OFF.

摘要翻译： 一种双CMOS电路包括第一双极型，第二双极晶体管和CMOS控制单元，用于根据施加到输入端的输入信号执行第一和第二双极晶体管的开关控制，并用于控制输出信号经由 输出端基于输入信号。 基于在第一双极晶体管截止时流过所述控制装置的电流，关断单元暂时性将第一双极晶体管的基极连接到低电位侧电源线，使得第一双极晶体管可 快速关闭。

公开(公告)号：US5138195A

公开(公告)日：1992-08-11

申请号：US599879

申请日：1990-10-19

申请人： Shinzou Satou ,  Kou Ebihara ,  Toru Nakamura ,  Toshiyuki Koreeda

发明人： Shinzou Satou ,  Kou Ebihara ,  Toru Nakamura ,  Toshiyuki Koreeda

IPC分类号： H03K19/013 ,  H03K19/0944

CPC分类号： H03K19/0136 ,  H03K19/09448

摘要： A Bi-CMOS logic circuit includes first and second bipolar transistors connected in series between a first power source and a second power source. An output signal is drawn from a connection node at which first and second bipolar transistors are connected in series. The Bi-CMOS logic circuit also includes a first impedance element, connected between a base and an emitter of the first bipolar transistor, providing a first impedance, and a second impedance element, connected between a base of the second bipolar transistor and an emitter thereof, providing a second impedance. Further, the Bi-CMOS logic circuit includes a first MOS transistor connected between the collector of the first bipolar transistor and the base thereof, a second MOS transistor connected between the collector of the second bipolar transistor and the base thereof, an input signal being applied to gates of the first and second MOS transistors; and a third MOS transistor connected between the base of the first bipolar transistor and the second power source. The third MOS transistor has the gate thereof connected to the base of the second bipolar transistor.

摘要翻译： Bi-CMOS逻辑电路包括串联连接在第一电源和第二电源之间的第一和第二双极晶体管。 从第一和第二双极晶体管串联连接的连接节点抽出输出信号。 Bi-CMOS逻辑电路还包括第一阻抗元件，连接在第一双极晶体管的基极和发射极之间，提供第一阻抗，第二阻抗元件连接在第二双极晶体管的基极与其发射极之间 ，提供第二阻抗。 此外，Bi-CMOS逻辑电路包括连接在第一双极晶体管的集电极及其基极之间的第一MOS晶体管，连接在第二双极晶体管的集电极及其基极之间的第二MOS晶体管，施加的输入信号 到第一和第二MOS晶体管的栅极; 以及连接在第一双极晶体管的基极和第二电源之间的第三MOS晶体管。 第三MOS晶体管的栅极连接到第二双极晶体管的基极。

公开(公告)号：US5097150A

公开(公告)日：1992-03-17

申请号：US525058

申请日：1990-05-18

申请人： Shinzou Satou ,  Kou Ebihara

发明人： Shinzou Satou ,  Kou Ebihara

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H03K19/09448 ,  H03K19/0136

摘要： A Bi-CMOS logic circuit includes a Bi-CMOS circuit which is composed of first and second bipolar transistors, first and second resistors, and first and second MOS transistors. An input signal is applied to the gates of the first and second MOS transistors, and an output signal is drawn from a connection node at which the first and second bipolar transistors are connected in series between first and second power sources. A third MOS transistor is connected between the collector and emitter of the first bipolar transistor. The input signal is applied to the gate of the third MOS transistor. In place of or in addition to the third MOS transistor, a fourth MOS transistor is provided which is connected between the collector and emitter of the second bipolar transistor. The third and fourth MOS transistors function to decrease roundings of rising and falling edges of the waveform of the output signal.

公开(公告)号：US5323065A

公开(公告)日：1994-06-21

申请号：US924941

申请日：1992-08-05

申请人： Kou Ebihara ,  Kunihiko Kawaguchi

发明人： Kou Ebihara ,  Kunihiko Kawaguchi

IPC分类号： H03K3/012 ,  H03K3/037 ,  H03K3/289 ,  H03K5/12

CPC分类号： H03K3/037 ,  H03K3/012

摘要： A semiconductor integrated circuit device includes a preceding circuit portion, a flip-flop circuit portion receiving complementary output signals of the preceding circuit portion, for latching data in accordance with the complementary output signals of the preceding circuit portion, and a compensation circuit portion receiving complementary output signals of the flip-flop circuit portion and receiving the complementary output signals of the preceding circuit portion without passing through the flip-flop circuit portion, for compensating driving power and decreasing a delay time of a specific phase. Therefore, the delay time of the semiconductor integrated circuit device can be decreased in one phase (specific phase).

摘要翻译： 一种半导体集成电路装置，包括前一电路部分，触发电路部分，接收前一电路部分的互补输出信号，用于根据前一电路部分的互补输出信号锁存数据;以及补偿电路部分， 输出触发电路部分的输出信号，并且不通过触发器电路部分接收前一电路部分的互补输出信号，用于补偿驱动功率并减小特定相位的延迟时间。 因此，可以在一相（特定相）中降低半导体集成电路器件的延迟时间。