公开(公告)号：US5612632A

公开(公告)日：1997-03-18

申请号：US346562

申请日：1994-11-29

申请人： Shivaling Mahant-Shetti ,  Kevin Ovens ,  Clive Bittlestone ,  Robert C. Martin ,  Robert J. Landers

发明人： Shivaling Mahant-Shetti ,  Kevin Ovens ,  Clive Bittlestone ,  Robert C. Martin ,  Robert J. Landers

IPC分类号： H03K3/037 ,  H03K3/356 ,  H03K19/173 ,  H03K19/00

CPC分类号： H03K3/356173 ,  H03K3/037 ,  H03K3/356156

摘要： A flip-flop includes a data storage node for driving an inverter (62) and transfer gate (64) combination to transfer data stored on the data node (60) to a master storage node (66). A master cross-coupled latch (68) has two cross-coupled inverters (72) and (74) connected thereto such that the master storage node (66) is only connected to one side of the latch (68). The data node (66) directly drives a slave stage comprised of an inverter (76) and transfer gate (78) which in turn drives a slave storage node (80). The slave storage node (80) is connected to a slave cross-coupled latch (82) comprised of cross-coupled inverters (86) and (88). The slave storage node (80) comprises the Q-output of the inverter. The data is transferred to storage node (66) on the negative going edge of the clock signal and latched thereto on the positive going edge of the clock signal. ON the positive going edge of the clock signal, data is transferred from the storage node (66) to the slave storage node (80) and then latched in the latch (82) on the negative going edge of the clock signal. This results in a minimum number of inverters, thus decreasing the Clock-to-Q time.

摘要翻译： 触发器包括用于驱动逆变器（62）和传送门（64）组合以将存储在数据节点（60）上的数据传送到主存储节点（66）的数据存储节点。 主交叉耦合锁存器（68）具有连接到其上的两个交叉耦合的反相器（72）和（74），使得主存储节点（66）仅连接到锁存器（68）的一侧。 数据节点（66）直接驱动由逆变器（76）和传输门（78）组成的从动级，后者又驱动从存储节点（80）。 从存储节点（80）连接到由交叉耦合的反相器（86）和（88）组成的从交叉耦合锁存器（82）。 从存储节点（80）包括逆变器的Q输出。 数据被传送到时钟信号的负向边缘上的存储节点（66），并在时钟信号的正向沿被锁存在存储节点（66）上。 在时钟信号的正向边缘上，数据从存储节点（66）传送到从存储节点（80），然后锁存在时钟信号的负沿的锁存器（82）中。 这导致最小数量的反相器，从而减少了Clock-to-Q时间。

公开(公告)号：US5430408A

公开(公告)日：1995-07-04

申请号：US259731

申请日：1994-06-14

申请人： Kevin Ovens ,  Clive Bittlestone ,  Bob Helmick

发明人： Kevin Ovens ,  Clive Bittlestone ,  Bob Helmick

IPC分类号： H03K17/041 ,  H03K17/567 ,  H03K17/04 ,  H03K17/12

CPC分类号： H03K17/04106 ,  H03K17/567

摘要： A transmission gate circuit 20 includes a pull-up control circuit 15, a pull-down control circuit 17, and an electrical switch 19. Pull-up control circuit 15 and electrical switch 19 provide fast, complete transition from low-to-high at the output of circuit 20 thus improving circuit 20 speed as well as improving the switching speed of subsequent gates. Pull-down control circuit 17 and electrical switch 19 provide complete transition from high-to-low at the output of circuit 20. Transmission gate circuit 17 also provides increased drive such that circuit 20 may provide a gate fanout increase of 3X.

摘要翻译： 传输门电路20包括上拉控制电路15，下拉控制电路17和电开关19.上拉控制电路15和电开关19提供从低到高的快速，完全的过渡 电路20的输出因此提高电路20的速度以及提高随后的门的切换速度。 下拉控制电路17和电开关19在电路20的输出处提供从高到低的完全转变。传输门电路17还提供增加的驱动，使得电路20可以提供3X的栅极扇出增加。

公开(公告)号：US5381455A

公开(公告)日：1995-01-10

申请号：US53941

申请日：1993-04-28

申请人： Kevin Ovens ,  Clive Bittlestone ,  Bob Helmick

发明人： Kevin Ovens ,  Clive Bittlestone ,  Bob Helmick

IPC分类号： G11C19/00

CPC分类号： G11C19/00

摘要： An interleaved shift register 20 includes a plurality of data storage elements 22a-22d having a common data input signal. Each of the plurality of data storage elements 22a-22d has an enable control input that is connected to one of a plurality of clock signals, each of the plurality of clock signals being incrementally out of phase with one another. Interleaved shift register 20 provides multiple data bits of the data signal to be stored within a single clock period of one of the plurality of clock signals, thus greatly improving the data rate without increasing the storage rate of the plurality of data storage elements 22a-22d.

摘要翻译： 交错移位寄存器20包括具有公共数据输入信号的多个数据存储元件22a-22d。 多个数据存储元件22a-22d中的每一个具有连接到多个时钟信号之一的使能控制输入，多个时钟信号中的每一个彼此逐渐地异相。 交错移位寄存器20提供要在多个时钟信号之一的单个时钟周期内存储的数据信号的多个数据位，从而大大提高数据速率，而不增加多个数据存储元件22a-22d的存储速率 。

公开(公告)号：US06614358B1

公开(公告)日：2003-09-02

申请号：US09649661

申请日：2000-08-29

申请人： Mike Hutchison ,  Kevin Ovens ,  Tom Shinham

发明人： Mike Hutchison ,  Kevin Ovens ,  Tom Shinham

IPC分类号： G08B522

CPC分类号： H05B33/0821 ,  G08G1/095 ,  H05B33/0851 ,  H05B33/089

摘要： A solid state light apparatus ideally suited for use in traffic control signals provided with optical feedback to achieve a constant light output, preferably by detecting back-scattered light from a diffuser centered above an LED array. The control logic allows for the LEDs to be individually driven, and having their drive characteristics changed over time to ensure a uniform beam of light is generated at an intensity meeting DOT standards, across the life of the device. The optical feedback also establishes the uniform beam intensity level as a function of sensed ambient light to discern day and night operation.

摘要翻译： 一种固态光装置，理想地适用于提供光反馈的交通控制信号，以实现恒定的光输出，优选地通过检测来自位于LED阵列上方的扩散器的反向散射光。 控制逻辑允许LED单独驱动，并且其驱动特性随着时间的推移而改变，以确保在设备的整个使用寿命期间以符合DOT标准的强度产生均匀的光束。 光学反馈还建立了均匀的光束强度水平作为感测到的环境光的函数，以辨别昼夜操作。

公开(公告)号：US20060049800A1

公开(公告)日：2006-03-09

申请号：US10933581

申请日：2004-09-03

申请人： Byron Reed ,  Kevin Ovens

发明人： Byron Reed ,  Kevin Ovens

IPC分类号： H02J7/00

CPC分类号： H02M3/1588 ,  H02M2001/0032 ,  Y02B70/1466 ,  Y02B70/16

摘要： Systems and methods are disclosed to mitigate power consumption in a power supply, such as when operating in a low power mode. One aspect of the present invention relates to a control system for a power supply. The system includes a bias generator that provides a bias signal operative to charge a storage device based on a control signal. During a low power mode, a control system provides the control signal with a predetermined duty cycle that is functionally related to a storage capacity of the storage device.

摘要翻译： 公开了系统和方法以减轻电源中的功率消耗，例如当以低功率模式操作时。 本发明的一个方面涉及一种用于电源的控制系统。 该系统包括偏置发生器，其提供基于控制信号对存储装置进行充电的偏置信号。 在低功率模式期间，控制系统向控制信号提供与存储装置的存储容量功能相关的预定占空比。

公开(公告)号：US20060025104A1

公开(公告)日：2006-02-02

申请号：US10901664

申请日：2004-07-29

申请人： Byron Reed ,  Kevin Ovens

发明人： Byron Reed ,  Kevin Ovens

IPC分类号： H04B1/16 ,  H04B1/38 ,  H04M1/00

CPC分类号： H02M3/156 ,  H02M2001/0025

摘要： Systems and methods are disclosed to mitigate a transient condition in electrical energy that is supplied to a load. A power supply system includes a converter that supplies regulated electrical energy to an associated load. A feedback network provides a reference signal based on the regulated electrical energy being supplied to the load, the regulator controlling the regulated electrical energy based on the reference signal. The feedback network is modified to adjust the reference signal so as to mitigate a transient condition in the regulated electrical energy.

摘要翻译： 公开了系统和方法以减轻提供给负载的电能中的瞬态状态。 电源系统包括向相关负载提供调节电能的转换器。 反馈网络基于提供给负载的调节电能提供参考信号，调节器基于参考信号来控制调节的电能。 修改反馈网络以调整参考信号，以便减轻调节电能中的瞬态状态。

公开(公告)号：US06452419B1

公开(公告)日：2002-09-17

申请号：US09834142

申请日：2001-04-12

申请人： Kevin Ovens

发明人： Kevin Ovens

IPC分类号： H03K190185

CPC分类号： G05F3/18

摘要： A stacked logic circuit (20) having a serially connected first logic circuit (12) operating off a first voltage differential and providing in series with a second logic circuit (14) operating off a second voltage differential. The second logic circuit being in series with the first logic circuit recycles the current of the first logic circuit. A low impedance shunt circuit (30) is provided in parallel with the first logic circuit (12) and shunts additional current required of and to the second logic circuit (14) from the single voltage source (VCC). A Zener diode (Z1) shunts current from the first logic circuit not required by the second logic circuit via a shunt node (N). The shunt circuit (30) includes a Darlington pair of transistors or a three terminal voltage regulator (42) and only shunts a very small amount of current to ground. The stacked logic circuit of the present invention efficiently uses current drawn by the single voltage source to reduce power consumption.

摘要翻译： 堆叠逻辑电路（20）具有串联连接的第一逻辑电路（12），其操作第一电压差并与第二电压差动作的第二逻辑电路（14）串联。 与第一逻辑电路串联的第二逻辑电路回收第一逻辑电路的电流。 提供与第一逻辑电路（12）并联的低阻分流电路（30），并从第一逻辑电路（VCC）分流所需的额外电流并向第二逻辑电路（14）分流。 齐纳二极管（Z1）通过分流节点（N）将来自第一逻辑电路的电流分流到第二逻辑电路不需要的电流。 分流电路（30）包括达林顿晶体管对或三端电压调节器（42），并且仅将非常少量的电流分流到地。 本发明的堆叠式逻辑电路有效地利用由单电源吸引的电流来降低功耗。

公开(公告)号：US20060022653A1

公开(公告)日：2006-02-02

申请号：US10901672

申请日：2004-07-29

申请人： Byron Reed ,  Kevin Ovens

发明人： Byron Reed ,  Kevin Ovens

IPC分类号： G05F1/40

CPC分类号： H02M3/158 ,  H02M2001/0045 ,  H02M2003/1566

摘要： Systems and methods are disclosed to mitigate transient electrical energy that is supplied to a load. A power supply system can include a regulator that supplies regulated electrical energy to an associated load based on an operating mode of the system. A supplemental power supply supplies supplemental electrical energy to the associated load that varies over time to mitigate transient electrical characteristics in the electrical energy being supplied to the associated load due to an operating mode transition of the power supply system.

摘要翻译： 公开了系统和方法以减轻提供给负载的瞬时电能。 电源系统可以包括调节器，其基于系统的操作模式将调节的电能提供给相关联的负载。 补充电源为相关联的负载提供补充电能，随着时间的推移而变化，以减轻由于电力供应系统的运行模式转变而被供应给相关负载的电能中的瞬时电特性。

公开(公告)号：US4956567A

公开(公告)日：1990-09-11

申请号：US310275

申请日：1989-02-13

申请人： Steven A. Hunley ,  Kevin Ovens

发明人： Steven A. Hunley ,  Kevin Ovens

IPC分类号： G11C11/417 ,  G05F3/22 ,  G11C11/414 ,  H01L21/8249 ,  H01L27/06 ,  H03K5/02 ,  H03K19/003 ,  H03K19/0175

CPC分类号： G05F3/225 ,  H03K19/00384 ,  H03K19/017518 ,  Y10S323/907

摘要： A temperature compensation circuit (FIG. 5a) has a controlled temperature compensated voltage drop across R1. A Schottky diode D1 is connected to the base of Q1 through resistor R1. The temperature coefficients of the base-emitter junction of Q1 and the diode D1 have a predetermined differential, preferably none. The forward voltage drop across D1 and the base-emitter junction are different, thereby establishing a controlled current through resistor R1 that is independent of temperature.

摘要翻译： 温度补偿电路（图5a）具有跨越R1的受控温度补偿电压降。 肖特基二极管D1通过电阻R1连接到Q1的基极。 Q1和二极管D1的基极 - 发射极结的温度系数具有预定的差值，优选为无。 D1和基极 - 发射极结之间的正向压降不同，从而通过电阻器R1建立与温度无关的受控电流。