公开(公告)号：US07687015B2

公开(公告)日：2010-03-30

申请号：US11282835

申请日：2005-11-21

申请人： Shotaro Watanabe ,  Yasuko Osaki ,  Naoyuki Tsuda ,  Kazunari Watanabe

发明人： Shotaro Watanabe ,  Yasuko Osaki ,  Naoyuki Tsuda ,  Kazunari Watanabe

IPC分类号： C04B35/64 ,  C03C14/00

CPC分类号： C04B35/465 ,  C03C10/0036 ,  C03C14/004 ,  C03C2214/20 ,  C04B35/117 ,  C04B35/4686 ,  C04B2235/3206 ,  C04B2235/3222 ,  C04B2235/3232 ,  C04B2235/3236 ,  C04B2235/3284 ,  C04B2235/3445 ,  C04B2235/3481 ,  C04B2235/365 ,  C04B2235/5445 ,  C04B2235/6025 ,  C04B2235/80 ,  C04B2235/94 ,  C04B2235/9607 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/4629 ,  H05K3/4688

摘要： A method for producing a laminated dielectric, which comprises laminating a raw material layer containing a high dielectric constant glass ceramic composition comprising from 30 to 70 mass % of a Ba—Ti compound powder having a Ti/Ba molar ratio of from 3.0 to 5.7 and from 30 to 70 mass % of an alkali free glass powder containing, by mol %, from 15 to 40% of SiO2, from 5 to 37% of B2O3, from 2 to 15% of Al2O3, from 1 to 25% of CaO+SrO, from 5 to 25% of BaO and from 25 to 50% of SiO2+Al2O3, and a raw material layer containing a low dielectric constant glass ceramic composition comprising from 10 to 70 mass % of a ceramic powder and from 30 to 90 mass % of an alkali free glass powder wherein SiO2+Al2O3 is at least 34 mol % and larger by at least 9 mol % than that in the above alkali free glass powder, followed by firing.

摘要翻译： 一种叠层电介质的制造方法，其特征在于，将包含30〜70质量％的Ti / Ba摩尔比为3.0〜5.7的Ba-Ti系化合物粉末的高介电常数玻璃陶瓷组合物的原料层层叠， 30〜70质量％的无碱玻璃粉末，其含有摩尔％，15〜40％的SiO 2，5〜37％的B 2 O 3，2〜15％的Al 2 O 3，1〜25％的CaO + SrO，BaO 5〜25％，SiO 2 + Al 2 O 3 25〜50％，以及含有10〜70质量％的陶瓷粉末和30〜90质量％的低介电常数玻璃陶瓷组合物的原料层 ％的无碱玻璃粉末，其中SiO 2 + Al 2 O 3比上述无碱玻璃粉末中至少34摩尔％且大至少9摩尔％，随后进行烧制。

公开(公告)号：US20060075782A1

公开(公告)日：2006-04-13

申请号：US11282835

申请日：2005-11-21

申请人： Shotaro Watanabe ,  Yasuko Osaki ,  Naoyuki Tsuda ,  Kazunari Watanabe

发明人： Shotaro Watanabe ,  Yasuko Osaki ,  Naoyuki Tsuda ,  Kazunari Watanabe

IPC分类号： C03B23/203 ,  C03B29/00

CPC分类号： C04B35/465 ,  C03C10/0036 ,  C03C14/004 ,  C03C2214/20 ,  C04B35/117 ,  C04B35/4686 ,  C04B2235/3206 ,  C04B2235/3222 ,  C04B2235/3232 ,  C04B2235/3236 ,  C04B2235/3284 ,  C04B2235/3445 ,  C04B2235/3481 ,  C04B2235/365 ,  C04B2235/5445 ,  C04B2235/6025 ,  C04B2235/80 ,  C04B2235/94 ,  C04B2235/9607 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/4629 ,  H05K3/4688

摘要： A method for producing a laminated dielectric, which comprises laminating a raw material layer containing a high dielectric constant glass ceramic composition comprising from 30 to 70 mass % of a Ba—Ti compound powder having a Ti/Ba molar ratio of from 3.0 to 5.7 and from 30 to 70 mass % of an alkali free glass powder containing, by mol %, from 15 to 40% of SiO2, from 5 to 37% of B2O3, from 2 to 15% of Al2O3, from 1 to 25% of CaO+SrO, from 5 to 25% of BaO and from 25 to 50% of SiO2+Al2O3, and a raw material layer containing a low dielectric constant glass ceramic composition comprising from 10 to 70 mass % of a ceramic powder and from 30 to 90 mass % of an alkali free glass powder wherein SiO2+Al2O3 is at least 34 mol % and larger by at least 9 mol % than that in the above alkali free glass powder, followed by firing.

摘要翻译： 一种叠层电介质的制造方法，其特征在于，将包含30〜70质量％的Ti / Ba摩尔比为3.0〜5.7的Ba-Ti系化合物粉末的高介电常数玻璃陶瓷组合物的原料层层叠， 30〜70质量％的无碱玻璃粉末，其含有摩尔％为15〜40％的SiO 2，5〜37％的B 2 O 3，2〜15％的Al 2 O 3， 2％〜3％，1％〜25％的CaO + SrO，5〜25％的BaO和25〜50％的SiO 2， + Al 2 O 3 3，以及包含10〜70质量％的陶瓷粉末和30〜90质量％的低介电常数玻璃陶瓷组合物的原料层 ％的无碱玻璃粉末，其中SiO 2 + Al 2 O 3 3％至少为34摩尔％且大于9摩尔％ 比上述无碱玻璃粉末，然后烧成。

公开(公告)号：US5170237A

公开(公告)日：1992-12-08

申请号：US608557

申请日：1990-11-02

申请人： Naoyuki Tsuda ,  Tsuneo Yamaguchi ,  Tadataka Kaneko

发明人： Naoyuki Tsuda ,  Tsuneo Yamaguchi ,  Tadataka Kaneko

IPC分类号： G01L9/00

CPC分类号： G01L9/0054 ,  G01L9/0042

摘要： A semiconductor pressure sensor comprising a diaphragm area formed on a semiconductor chip, a plurality of gauge resistances arranged on one face of the diaphragm area to form a bridge circuit, and an oxide film formed on the top of the diaphragm area, wherein at least one additional pattern is formed in a portion of said diaphragm area other than said gauge resistances. The thickness of the oxide film on said additional pattern is smaller than the thickness of the oxide film on portions other than said gauge resistances and said additional pattern.

公开(公告)号：US4064525A

公开(公告)日：1977-12-20

申请号：US696389

申请日：1976-06-15

申请人： Gota Kano ,  Naoyuki Tsuda ,  Hitoo Iwasa

发明人： Gota Kano ,  Naoyuki Tsuda ,  Hitoo Iwasa

IPC分类号： H01L29/78 ,  G05F3/24 ,  H01L21/331 ,  H01L21/337 ,  H01L21/822 ,  H01L27/04 ,  H01L27/098 ,  H01L29/73 ,  H01L29/80 ,  H01L29/808 ,  H01L29/86 ,  H03H11/52 ,  H01L27/02

CPC分类号： H01L27/098 ,  H03H11/52 ,  Y10S148/018 ,  Y10S148/049 ,  Y10S148/151

摘要： A pair of field-effect transistors (hereinafter referred to as FETs) of p-channel type and n-channel type, respectively, both to be electrically actuated in a depletion mode, are formed on a single semiconductor substrate, for instance, a single silicon substrate, and both sources or both drains are connected to each other, or the source of one FET and the drain of the other FET are connected to each other, whereby the pair of FETs are series-connected, and the gate electrode of each FET is connected to the drain electrode or the source electrode that is not series connected in the abovementioned way, respectively, of the other FET. When a voltage of specified range is applied across both non-series-connected electrodes, i.e., the two external terminals, the resulting voltage-current characteristic presents a so-called dynatron-type characteristic, producing a negative-resistance phenomenon over a fairly wide range of applied voltage.Since this device is, as seen from outside as one device, a two-terminal device constituted on a single substrate, it is not only fit to be highly integrated, but also able to produce a state of virtually zero value of cut-off current. Consequently, this device can be utilized for switching, memorization, large amplitude oscillation, and other various uses.

摘要翻译： 在单个半导体衬底上形成分别以耗尽模式电致动的p沟道型和n沟道型的一对场效应晶体管（以下称为FET），例如单个 硅衬底，两个源极或两个漏极彼此连接，或者一个FET的源极和另一个FET的漏极彼此连接，由此一对FET串联连接，并且每个FET的栅极电极 FET分别与另一个FET分别以上述方式串联的漏电极或源极连接。 当在两个非串联电极（即两个外部端子）上施加规定范围的电压时，所得到的电压 - 电流特性呈现所谓的电压特性，在相当宽的范围内产生负电阻现象 施加电压范围。