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    Structure and method of array multiplication
    1.
    发明授权
    Structure and method of array multiplication 失效
    阵列乘法的结构和方法

    公开(公告)号：US5914892A

    公开(公告)日：1999-06-22

    申请号：US964040

    申请日：1997-11-04

    Applicant: Shyh-Jye Wang ,  Hsing-Chien Huang ,  Chi-Chiang Wu

    Inventor： Shyh-Jye Wang ,  Hsing-Chien Huang ,  Chi-Chiang Wu

    IPC: G06F7/52

    CPC classification number: G06F7/5312

    Abstract: A structure and method for forming multiplication of a b-bit multiplicand X and a b-bit multiplier Y to generate a product P is disclosed. The present invention includes cells C.sub.mn configured in a b.times.b array, and pieces of means for generating partial product X.sub.mn, wherein outputs of the partial product generating means are connected to first inputs of the cells respectively. The second inputs of the cells C.sub.mn, where m=0, 1, 2, . . . , b-2, and n=1, 2, . . . , b-1, are connected to first outputs of the cells C.sub.m+1, n-1 respectively, and the second inputs of the cells C.sub.b-1, n, where n=1, 2, . . . , b-1, are connected to second outputs of the cells C.sub.n-1, b-1 respectively. Further, the third inputs of the cells C.sub.mn, where m=0, 1, 2, . . . , b-1, and n=2, 3, . . . , b-1, are connected to the second outputs of the cells C.sub.m, n-1. Therefore, a portion of the product P.sub.f, where f=0, 1, . . . , b-1, comes from the first outputs of the cells C.sub.0, f, another portion of the product P.sub.g, where g=b, b+1, . . . , 2b-1, comes from the first outputs of the cells C.sub.g-3, b-1, and a most significant bit P.sub.2b-1 of the product comes from the second output of the cell C.sub.b-1,b-1.

    Abstract translation: 公开了一种用于形成b比特被乘数X和b比特乘法器Y的乘法以产生乘积P的结构和方法。 本发明包括以bxb阵列配置的单元Cmn和用于产生部分乘积Xmn的装置，其中部分乘积生成装置的输出分别连接到单元的第一输入。 单元格Cmn的第二个输入，其中m = 0,1,2。 。 。 ，b-2，n = 1,2。 。 。 ，b-1分别连接到单元格Cm + 1，n-1的第一输出端和单元格Cb-1，n的第二输入端，其中n = 1,2。 。 。 ，b-1分别连接到单元Cn-1，b-1的第二输出。 此外，单元格Cmn的第三输入，其中m = 0,1,2。 。 。 ，b-1，n = 2,3。 。 。 ，b-1连接到单元格Cm，n-1的第二输出端。 因此，产品Pf的一部分，其中f = 0,1，...。 。 。 ，b-1来自单元格C0，f的第一个输出，乘积Pg的另一部分，其中g = b，b + 1，...。 。 。 ，2b-1来自小区Cg-3，b-1的第一输出，并且产品的最高有效位P2b-1来自小区Cb-1，b-1的第二输出。

    Programmable non-overlap clock generator
    2.
    发明授权
    Programmable non-overlap clock generator 失效
    可编程非重叠时钟发生器

    公开(公告)号：US5977809A

    公开(公告)日：1999-11-02

    申请号：US968558

    申请日：1997-11-12

    Applicant: Shyh-Jye Wang ,  Chi-Chiang Wu ,  Wen-Hsiang Huang

    Inventor： Shyh-Jye Wang ,  Chi-Chiang Wu ,  Wen-Hsiang Huang

    IPC: H03H11/16 ,  H03K5/00 ,  H03K5/13 ,  H03K5/151

    CPC classification number: H03K5/1515 ,  H03K5/133 ,  H03K2005/00058

    Abstract: A programmable non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate, whose first input terminal is coupled to receive an inverted signal of the primary clock signal. Further, the first input terminal of a second logic gate is coupled to receive the primary clock signal. A first programmable delay means, connected between an output of the first logic gate and the second input terminal of the second logic gate, is used to delay an output signal from the first logic gate a predetermined amount of time according to the selection signal. Moreover, a second programmable delay means, connected between an output of the second logic gate and the second input terminal of the first logic gate, is used to delay an output signal from the second logic gate a predetermined amount of time according to the selection signal. The programmable non-overlap clock generator therefore generates a first clock signal from the output of the first logic gate, and generates a second clock signal from the output of the second logic gate, wherein the first clock signal and the second clock signal are not logically active at the same time.

    Abstract translation: 公开了可编程非重叠时钟发生器。 该时钟发生器包括用于提供主时钟信号的主时钟信号输入端和用于提供至少一个选择信号的选择信号输入端。 本发明还包括第一逻辑门，其第一输入端被耦合以接收主时钟信号的反相信号。 此外，第二逻辑门的​​第一输入端耦合以接收主时钟信号。 连接在第一逻辑门的输出和第二逻辑门的​​第二输入端之间的第一可编程延迟装置用于根据选择信号将来自第一逻辑门的输出信号延迟预定的时间量。 此外，连接在第二逻辑门的​​输出和第一逻辑门的第二输入端之间的第二可编程延迟装置用于根据选择信号将来自第二逻辑门的​​输出信号延迟预定的时间量 。 可编程非重叠时钟发生器因此从第一逻辑门的输出产生第一时钟信号，并且从第二逻辑门的​​输出产生第二时钟信号，其中第一时钟信号和第二时钟信号不是逻辑地 同时活跃。

    MESSAGE-TRIGGERED VOICE COMMAND INTERFACE IN PORTABLE ELECTRONIC DEVICES
    3.
    发明申请
    MESSAGE-TRIGGERED VOICE COMMAND INTERFACE IN PORTABLE ELECTRONIC DEVICES 审中-公开
    消息触发的便携式电子设备中的语音接口

    公开(公告)号：US20150213801A1

    公开(公告)日：2015-07-30

    申请号：US14677988

    申请日：2015-04-03

    Applicant: Shyh-Jye Wang ,  Chi-Ping Chung

    Inventor： Shyh-Jye Wang ,  Chi-Ping Chung

    IPC: G10L17/22 ,  G10L15/08

    CPC classification number: G10L17/22 ,  G10L15/005 ,  G10L15/08 ,  G10L15/22 ,  H04M1/271 ,  H04M1/6075 ,  H04M1/72519 ,  H04M1/72552 ,  H04M2201/40 ,  H04M2250/74 ,  H04W52/0254 ,  H04W52/028 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/164 ,  Y02D70/26

    Abstract: The embodiments provided herein are directed to a system and method of message-triggered voice command interface in portable electronic devices. The voice command interface is normally not activated until a message (e.g., an e-mail, a text message, or a voice mail) has been received by a portable electronic device. The arriving of a message is used to trigger the voice command interface by activating one or more speech recognition routines in a predetermined time period corresponding to the one or more speech recognition routines. The voice command interface come to an end when the predetermined time period expires or the user has no further commands.

    Abstract translation: 本文提供的实施例涉及便携式电子设备中的消息触发语音命令接口的系统和方法。 在通过便携式电子设备接收到消息（例如，电子邮件，文本消息或语音邮件）之前，语音命令接口通常不被激活。 通过在对应于一个或多个语音识别例程的预定时间段内激活一个或多个语音识别例程，将消息的到达用于触发语音命令接口。 当预定时间段到期或用户没有进一步的命令时，语音命令接口结束。

    Power-on reset circuit without an RC Network
    4.
    发明授权
    Power-on reset circuit without an RC Network 失效
    没有RC网络的上电复位电路

    公开(公告)号：US5874843A

    公开(公告)日：1999-02-23

    申请号：US864661

    申请日：1997-05-28

    Applicant: Shyh-Jye Wang

    Inventor： Shyh-Jye Wang

    IPC: H03K17/22 ,  H03K3/356

    CPC classification number: H03K17/223

    Abstract: A power-on reset circuit (28) is disclosed. The circuit includes a first stage circuit (30) and a second stage circuit (32). The first stage circuit includes an input terminal coupled to receive an input signal, a latch for detecting a power-on condition, and an output terminal for providing a first stage circuit output signal. The first stage circuit output signal remains in a first state after detection of the power-on condition. The second stage circuit includes an input terminal coupled to receive the first stage circuit output signal, a latch for detecting the power-on condition, and an output terminal for providing a second stage circuit output signal. The second stage circuit output signal remains in the first state after detection of the power-on condition. The first stage circuit output signal changes state from the first state to a second state when the input signal changes state from the second state to the first state, and the second stage circuit output signal changes state from the first state to the second state only the first time that the first stage circuit output signal changes state from the first state to the second state.

    Abstract translation: 公开了一种上电复位电路（28）。 电路包括第一级电路（30）和第二级电路（32）。 第一级电路包括耦合以接收输入信号的输入端子，用于检测通电状态的锁存器以及用于提供第一级电路输出信号的输出端子。 在检测到通电状态之后，第一级电路输出信号保持在第一状态。 第二级电路包括耦合以接收第一级电路输出信号的输入端子，用于检测通电状态的锁存器和用于提供第二级电路输出信号的输出端子。 在检测到通电状态之后，第二级电路输出信号保持在第一状态。 当输入信号从第二状态改变到第一状态时，第一级电路输出信号将状态从第一状态改变到第二状态，并且第二级电路输出信号仅将状态从第一状态改变到第二状态 第一级电路输出信号首先将状态从第一状态改变到第二状态。

    Self-setup non-overlap clock generator
    7.
    发明授权
    Self-setup non-overlap clock generator 失效
    自设置非重叠时钟发生器

    公开(公告)号：US5867453A

    公开(公告)日：1999-02-02

    申请号：US019686

    申请日：1998-02-06

    Applicant: Shyh-Jye Wang ,  Chi-Chiang Wu ,  Hsing-Chien Huang

    Inventor： Shyh-Jye Wang ,  Chi-Chiang Wu ,  Hsing-Chien Huang

    IPC: H03K5/151 ,  G04F8/00 ,  H03K3/037 ,  H03K5/13

    CPC classification number: H03K5/1515

    Abstract: A self-setup non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate having a first input terminal coupled to receive an inverted signal of the primary clock signal. Further, a second logic gate is provided, having a first input terminal coupled to receive the primary clock signal. A first programmable delay portion is used to delay an output signal from the first logic gate an amount of time according to the selection signal, and a second programmable delay portion is used to delay an output signal from the second logic gate a predetermined amount of time according to the selection signal. Therefore, a first clock signal is generated from the output of the first logic gate, and a second clock signal is generated from the output of the second logic gate. Particularly, the present invention includes a test circuit to determine whether a non-overlap space between the first clock signal and the second clock signal conforms to a predetermined value. Finally, a selector is used to generate the at least one selection signal in response to at least one output of the test circuit such that a smallest value out of all possible non-overlap spaces is chosen.

    Abstract translation: 公开了一种自建非重叠时钟发生器。 该时钟发生器包括用于提供主时钟信号的主时钟信号输入端和用于提供至少一个选择信号的选择信号输入端。 本发明还包括具有耦合以接收主时钟信号的反相信号的第一输入端的第一逻辑门。 此外，提供了第二逻辑门，其具有耦合以接收主时钟信号的第一输入端。 第一可编程延迟部分用于根据选择信号将来自第一逻辑门的输出信号的时间量延迟，并且第二可编程延迟部分用于将来自第二逻辑门的​​输出信号延迟预定的时间量 根据选择信号。 因此，从第一逻辑门的输出产生第一时钟信号，并且从第二逻辑门的​​输出产生第二时钟信号。 特别地，本发明包括测试电路，用于确定第一时钟信号和第二时钟信号之间的非重叠空间是否符合预定值。 最后，选择器用于响应于测试电路的至少一个输出而产生至少一个选择信号，使得选择所有可能的非重叠空间中的最小值。

    MESSAGE-TRIGGERED VOICE COMMAND INTERFACE IN PORTABLE ELECTRONIC DEVICES
    9.
    发明申请
    MESSAGE-TRIGGERED VOICE COMMAND INTERFACE IN PORTABLE ELECTRONIC DEVICES 审中-公开
    消息触发的便携式电子设备中的语音接口

    公开(公告)号：US20140337028A1

    公开(公告)日：2014-11-13

    申请号：US13892299

    申请日：2013-05-12

    Applicant: Shyh-Jye Wang ,  Chi-Ping Chung

    Inventor： Shyh-Jye Wang ,  Chi-Ping Chung

    IPC: G10L15/22 ,  G10L15/00

    CPC classification number: G10L17/22 ,  G10L15/005 ,  G10L15/08 ,  G10L15/22 ,  H04M1/271 ,  H04M1/6075 ,  H04M1/72519 ,  H04M1/72552 ,  H04M2201/40 ,  H04M2250/74 ,  H04W52/0254 ,  H04W52/028 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/164 ,  Y02D70/26

    Abstract: The embodiments provided herein are directed to a system and method of message-triggered voice command interface in portable electronic devices. The voice command interface is normally not activated until a message (e.g., an e-mail, a text message, or a voice mail) has been received by a portable electronic device. The arriving of a message is used to trigger the voice command interface by activating one or more speech recognition routines in a predetermined time period corresponding to the one or more speech recognition routines. The voice command interface come to an end when the predetermined time period expires or the user has no further commands.

    Abstract translation: 本文提供的实施例涉及便携式电子设备中的消息触发语音命令接口的系统和方法。 在通过便携式电子设备接收到消息（例如，电子邮件，文本消息或语音邮件）之前，语音命令接口通常不被激活。 通过在对应于一个或多个语音识别例程的预定时间段内激活一个或多个语音识别例程，将消息的到达用于触发语音命令接口。 当预定时间段到期或用户没有进一步的命令时，语音命令接口结束。

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