公开(公告)号：US5055895A

公开(公告)日：1991-10-08

申请号：US433976

申请日：1989-11-09

申请人： Sigeo Akiyama ,  Masahiko Suzumura ,  Takeshi Nobe

发明人： Sigeo Akiyama ,  Masahiko Suzumura ,  Takeshi Nobe

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/7802 ,  H01L29/42368 ,  H01L29/7838 ,  Y10S148/126

摘要： A double-diffused metal-oxide-semiconductor field effect transistor (DMOSFET) device comprising an insulating layer having an opening on the top surface of a semiconductor wafer, channel regions and well regions and source regions formed through two stage deffusions of impurity materials respectively of a different conductivity type from and the same conductivity type as the wafer and carried out through the opening, and further comprising gate, source and drain electrodes which are formed after mashes provided on a surface area where the drain regions and the source electrode regions that are to be connected to the well regions and source regions and a further ion-implantation of an impurity material of the same conductivity type as the wafer into the channel regions, with the threshold voltage controlled to achieve a depletion type. The channel regions are relatively lower in the carrier corcentration than the other parts in the well regions to achieve a high breakdown voltage notwithstanding that the device is of the depletion type.

公开(公告)号：US4902636A

公开(公告)日：1990-02-20

申请号：US294787

申请日：1989-01-09

申请人： Sigeo Akiyama ,  Masahiko Suzumura ,  Takeshi Nobe

发明人： Sigeo Akiyama ,  Masahiko Suzumura ,  Takeshi Nobe

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/7802 ,  H01L29/42368 ,  H01L29/7838 ,  Y10S148/126

摘要： A method for manufacturing double-diffused metal-oxide-semiconductor field effect transistor (DMOSFET) device is to form an insulating layer having an opening in top surface on a semiconductor wafer, channel regions and well regions and source regions through two stage diffusions of impurity materials respectively of a different conductivity type from and the same conductivity type as the wafer and carried out through the opening, and further gate, source and drain electrodes are formed after masks provided on a surface area where the drain regions and the source electrode regions that are to be connected to the well regions and source regions and a further ion-implantation of an impurity material of the same conductivity type as the wafer into the channel regions, with the threshold voltage controlled to achieve a depletion type. The channel regions are relatively lower in the carrier concentration than the other parts in the well regions to achieve a high breakdown voltage notwithstanding that the device is of the depletion type.

摘要翻译： 制造双扩散金属氧化物半导体场效应晶体管（DMOSFET）器件的方法是通过两级杂质形成在半导体晶片，沟道区域，阱区域和源极区域的顶表面上具有开口的绝缘层 分别具有与晶片不同的导电类型的材料和与晶片相同的导电类型的材料，并通过开口进行，并且在设置在漏极区域和源极电极区域的表面区域上的掩模之后形成另外的栅极，源极和漏极电极， 将其连接到阱区域和源极区域以及将与晶片相同的导电类型的杂质材料进一步离子注入沟道区域中，其中阈值电压被控制以实现耗尽型。 沟道区域的载流子浓度相对于阱区域中的其它部分相对较低，以达到高的击穿电压，尽管该装置是耗尽型的。

公开(公告)号：US5296723A

公开(公告)日：1994-03-22

申请号：US909846

申请日：1992-07-07

申请人： Takeshi Nobe ,  Sigeo Akiyama

发明人： Takeshi Nobe ,  Sigeo Akiyama

IPC分类号： H01L27/06 ,  H01L31/12

CPC分类号： H01L27/0629

摘要： A low output capacitance, double-diffused field effect transistor effectively realizes the reduction in the output capacitance, by providing a drain electrode on one surface of a first conduction type semiconductor substrate, forming on the other surface of the substrate, through a double diffusion, second conduction type well regions and first conduction type source regions for connection therewith of a source electrode, forming channel regions in surface zone of the well regions disposed between first conduction type zone of the semiconductor substrate and the source regions, above which channel regions being provided gate electrodes through an insulating film, forming a guard ring region surrounding the well regions, and connecting at least one capacitance component means to the gate electrodes.

摘要翻译： 低输出电容双扩散场效应晶体管通过在第一导电型半导体衬底的一个表面上设置漏电极，通过双扩散在衬底的另一表面上形成，有效地实现了输出电容的减小， 第二导电型阱区域和与源电极连接的第一导电型源极区域，在设置在半导体衬底的第一导电类型区域和源极区域之间的阱区域的表面区域中形成沟道区域，在其上方设置沟道区域 通过绝缘膜形成栅电极，形成围绕阱区的保护环区域，以及将至少一个电容分量装置连接到栅电极。

公开(公告)号：US5278422A

公开(公告)日：1994-01-11

申请号：US935413

申请日：1992-08-26

申请人： Fumio Kato ,  Sigeo Akiyama ,  Masahiro Izumi ,  Noriteru Furumoto

发明人： Fumio Kato ,  Sigeo Akiyama ,  Masahiro Izumi ,  Noriteru Furumoto

IPC分类号： H03K17/0412 ,  H03K17/16 ,  H03K17/785 ,  G02B27/00 ,  H03K3/42

CPC分类号： H03K17/163 ,  H03K17/04123 ,  H03K17/785

摘要： A solid state relay circuit includes a MOSFET receiving a photovoltaic output generated across a photovoltaic diode array responsive to a light signal from a light emitting element, a control electrode of a normally ON type driving transistor made to be at a high impedance state by a voltage generated across an impedance element connected in series to the photovoltaic diode array upon application of the photovoltaic output across the gate and source of the MOSFET and at a low impedance state upon disappearance of the photovoltaic output is connected to a connecting point between the diode array and the impedance element, and the driving transistor is connected across the gate and source of the MOSFET with a resistor interposed. A falling gradient of output signal upon being turned OFF of the relay circuit is made thereby sufficiently gentle, and relay operation upon being turned OFF can be minimized in response time.

摘要翻译： 固态继电器电路包括：MOSFET接收光电二极管阵列产生的光电输出，该光伏输出响应于来自发光元件的光信号，正常导通型驱动晶体管的控制电极被制成处于高阻抗状态的电压 在跨越MOSFET的栅极和源极施加光伏输出并且在光伏输出消失时处于低阻抗状态的阻抗元件上串联连接到光伏二极管阵列的阻抗元件连接到二极管阵列和 阻抗元件和驱动晶体管连接在MOSFET的栅极和源极之间，并插入电阻器。 使继电器电路断开时的输出信号的下降斜率足够平缓，并且在关断时的继电器动作可以在响应时间内最小化。

公开(公告)号：US5420046A

公开(公告)日：1995-05-30

申请号：US339293

申请日：1994-11-10

申请人： Sigeo Akiyama ,  Fumio Kato ,  Kiyoshi Hosotani ,  Masato Miyamoto

发明人： Sigeo Akiyama ,  Fumio Kato ,  Kiyoshi Hosotani ,  Masato Miyamoto

IPC分类号： H01L31/111 ,  H01L49/00

CPC分类号： H01L31/1113

摘要： A method for manufacturing an optically triggered lateral thyristor is to form an anode region by providing a first opening in an insulating layer formed on a semiconductor substrate, a diffusion layer by providing a second opening in the insulating layer to be spaced from the anode region, a base-forming region by providing a third opening in the insulating layer externally adjacent to the second opening, and a base region and simultaneously a cathode region by means of double diffusion through the third opening, the base region having a lateral width determined by a diffusion difference between the base and cathode regions for effective minimization of the width.

摘要翻译： 一种用于制造光学触发的横向晶闸管的方法是通过在绝缘层中设置与阳极区间隔开的第二开口，在半导体衬底上形成绝缘层中的第一开口，扩散层来形成阳极区域， 通过在与第二开口相邻的绝缘层中设置第三开口的基底形成区域和通过第三开口的双扩散同时存在阴极区域，基底区域具有由 基极和阴极区之间的扩散差用于有效地最小化宽度。

公开(公告)号：US4804866A

公开(公告)日：1989-02-14

申请号：US26994

申请日：1987-03-10

申请人： Sigeo Akiyama

发明人： Sigeo Akiyama

IPC分类号： H03K17/687 ,  H01L27/142 ,  H01L31/02 ,  H01L31/167 ,  H03K17/0412 ,  H03K17/785 ,  H03K17/78

CPC分类号： H03K17/04123 ,  H01L31/02019 ,  H01L31/0475 ,  H01L31/167 ,  H03K17/785 ,  Y02E10/50 ,  Y10S136/293 ,  Y10T307/773

摘要： A solid state relay includes a MOS FET receiving a photovoltaic output generated across a photovoltaic diode array responsive to a light signal from a light-emitting element, and a normally ON driving transistor connected to the MOS FET, the driving transistor being connected at control electrode to a connection point between the photovoltaic diode array and an impedance element to be biased by a voltage generated across the impedance element during generation of the photovoltaic output across the photovoltaic diode array to have a high impedance state, whereby the relay can be prevented from providing at output terminals any intermediate state between ON and OFF states even when an input current to the relay is in lower range, and a high speed relay operation is realized.

摘要翻译： 固态继电器包括MOS FET，其响应于来自发光元件的光信号而接收在光电二极管阵列上产生的光伏输出，以及连接到MOS FET的正常导通驱动晶体管，驱动晶体管连接在控制电极 到光伏二极管阵列和阻抗元件之间的连接点，以在跨越光伏二极管阵列的光伏输出产生期间被跨过阻抗元件产生的电压偏置以具有高阻抗状态，由此可以防止继电器提供 在输出端子处于ON和OFF状态之间的任何中间状态，即使当到继电器的输入电流处于较低范围内时，也实现了高速继电器操作。

公开(公告)号：US4873202A

公开(公告)日：1989-10-10

申请号：US268215

申请日：1988-11-07

申请人： Sigeo Akiyama

发明人： Sigeo Akiyama

IPC分类号： H03K17/687 ,  H01L27/142 ,  H01L31/02 ,  H01L31/167 ,  H03K17/0412 ,  H03K17/785

CPC分类号： H03K17/04123 ,  H01L31/02019 ,  H01L31/0475 ,  H01L31/167 ,  H03K17/785 ,  Y02E10/50 ,  Y10S136/293 ,  Y10T307/773

摘要： A solid state relay includes a MOS FET receiving a photovoltaic output generated across a photovoltaic diode array responsive to a light signal from a light-emitting element, and a normally ON driving transistor connected to the MOS FET, the driving transistor being connected at control electrode to a connection point between the photovoltaic diode array and an impedance element to be biased by a voltage generated across the impedence element during generation of the photovoltaic output across the photovoltaic diode array to have a high impedance state, whereby the relay can be prevented from providing at output terminals any intermediate state between ON and OFF states even when an input current to the relay is in lower range, and a high speed relay operation is realized.

摘要翻译： 固态继电器包括MOS FET，其响应于来自发光元件的光信号而接收在光电二极管阵列上产生的光伏输出，以及连接到MOS FET的正常导通驱动晶体管，驱动晶体管连接在控制电极 到太阳能二极管阵列和阻抗元件之间的连接点，以在跨越光伏二极管阵列的光伏输出产生期间被跨越阻抗元件产生的电压偏置以具有高阻抗状态，由此可以防止继电器提供 在输出端子处于ON和OFF状态之间的任何中间状态，即使当到继电器的输入电流处于较低范围内时，也实现了高速继电器操作。