公开(公告)号：US10833682B1

公开(公告)日：2020-11-10

申请号：US16582266

申请日：2019-09-25

Applicant: Silicon Laboratories Inc.

Inventor： Timothy A. Monk ,  Douglas F. Pastorello

IPC: H03L7/06 ,  H03L7/081 ,  H03L7/197 ,  H03L7/093

Abstract: A clock generator includes an interpolative divider including a phase interpolator and a multi-modulus divider. The interpolative divider is configured to generate an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal. The clock generator includes a calibration circuit configured to generate the phase interpolator calibration signal based on the clock signal, the output clock signal and a phase interpolator code. The calibration circuit includes a phase-locked loop configured to generate a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal. The calibration circuit includes an adaptive loop configured to generate the phase interpolator calibration signal based on the digital phase error signal.

公开(公告)号：US10819353B1

公开(公告)日：2020-10-27

申请号：US16593473

申请日：2019-10-04

Applicant: Silicon Laboratories Inc.

Inventor： Timothy A. Monk ,  Douglas F. Pastorello

IPC: H03L7/08 ,  H03L7/087 ,  H03L7/22 ,  H03L7/23 ,  H03L7/093 ,  G01R31/317

Abstract: A spur target frequency is periodically determined to cancel a spur using a spur cancellation circuit in a first phase-locked loop (PLL) in a system with at least a second PLL that is in lock with the first PLL. The spur target frequency is periodically determined utilizing divide ratios of the first PLL and the second PLL to determine the updated spur target frequency. As one or more of the divide ratios change, the spur frequency changes and the spur target frequency is updated to reflect the change.

公开(公告)号：US09588497B1

公开(公告)日：2017-03-07

申请号：US15221078

申请日：2016-07-27

Applicant: Silicon Laboratories Inc.

Inventor： Timothy A. Monk ,  Rajesh Thirugnanam ,  Douglas F. Pastorello

IPC: H03M1/50 ,  G04F10/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/10

CPC classification number: G04F10/005 ,  H03L7/093 ,  H03L7/1075 ,  H03L7/1974 ,  H03L2207/50 ,  H03M1/60 ,  H03M1/804

Abstract: A feedback loop includes an oscillator-based analog-to-digital converter configured to convert an analog signal to a first digital value and a second digital value. The oscillator-based analog-to-digital converter includes a first oscillator having a first oscillation frequency configured to generate a first digital value based on a first signal component of the analog signal. The oscillator-based analog-to-digital converter includes a second oscillator having a second oscillation frequency configured to generate a second digital value based on a second signal component of the analog signal. The first and second signal components are complementary signal components. The feedback loop includes a combiner configured to generate a digital value based on the first digital value, the second digital value, and an offset code. The offset code has a value that increases a difference between the first oscillation frequency and the second oscillation frequency.

Abstract translation: 反馈环路包括基于振荡器的模拟 - 数字转换器，其被配置为将模拟信号转换为第一数字值和第二数字值。 基于振荡器的模数转换器包括具有第一振荡频率的第一振荡器，其被配置为基于模拟信号的第一信号分量产生第一数字值。 基于振荡器的模数转换器包括具有第二振荡频率的第二振荡器，其被配置为基于模拟信号的第二信号分量产生第二数字值。 第一和第二信号分量是互补信号分量。 反馈回路包括配置成基于第一数字值，第二数字值和偏移码产生数字值的组合器。 偏移码具有增加第一振荡频率和第二振荡频率之间的差的值。

公开(公告)号：US10511312B1

公开(公告)日：2019-12-17

申请号：US16456195

申请日：2019-06-28

Applicant: Silicon Laboratories Inc.

Inventor： Douglas F. Pastorello ,  Timothy Monk ,  Ping Lu ,  Michael Lu

IPC: H03L7/10 ,  H03L7/081 ,  H03K3/037 ,  H03K5/00 ,  G06F1/12 ,  G06F1/10 ,  H03L7/093

Abstract: A chip having output synchronization includes a phase detector for receiving an external reference clock signal, an input delay path coupled to an output of the phase detector and having an output for providing an internal reference clock signal, an output delay path coupled to the output of the input delay path and having an output coupled to a feedback input of the phase detector, a phase adjustment circuit having a first input coupled to the output of the input delay path, a second input for receiving a local clock signal, and an output coupled to the control input of the input delay path, and a synchronization capture circuit having a first input coupled to the output of said input delay path, a second input for receiving the local clock signal, a third input for receiving a synchronization signal, and an output for providing a synchronization trigger signal.

公开(公告)号：US20140118172A1

公开(公告)日：2014-05-01

申请号：US13664902

申请日：2012-10-31

Applicant: SILICON LABORATORIES INC.

Inventor： Xue-Mei Gong ,  Douglas F. Pastorello

IPC: H03M1/66

CPC classification number: H03M1/0673 ,  H03M1/0665 ,  H03M1/74 ,  H03M3/464 ,  H03M1/66 ,  H03M1/46

Abstract: A technique includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The technique includes generating the plurality of control signals based on the digital code, a random digital code having a number of bits based on a feedback signal, and an indicator of a second sequence of unit elements of the plurality of unit elements enabled in response to a prior digital code.

Abstract translation: 一种技术包括：响应于多个控制信号，选择性地启用数模转换器的多个单位元件的单元的第一序列将数字代码转换成多个模拟信号。 多个模拟信号中的多个控制信号和各个模拟信号的单独控制信号对应于多个单位元件中的相应单元。 该技术包括基于数字码产生多个控制信号，基于反馈信号具有多个位的随机数字码，以及响应于所述多个单元的单元的第二序列的指示符 以前的数字代码。