中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.013 seconds)

    DATA TRANSMISSION CIRCUIT
    1.
    发明申请
    DATA TRANSMISSION CIRCUIT 有权

    公开(公告)号：US20210091804A1

    公开(公告)日：2021-03-25

    申请号：US17030654

    申请日：2020-09-24

    Applicant: Silicon Works Co., Ltd.

    Inventor： Sang Hoon Paik ,  Jeong Hoon Nam ,  Yong Hwan Moon

    IPC: H04B1/04 ,  H03K17/687

    Abstract: A data transmission circuit which is improved to be capable of supporting a data transmission mode appropriate for an interface or an application depending on the selection of an option. The data transmission circuit includes a pre-driver configured to output a first differential driving signal, a second differential driving signal and pre-emphasis control signals by using a first differential data signal, a second differential data signal and option signals; a main driver configured to output a first differential transmission signal and a second differential transmission signal by using the first differential driving signal and the second differential driving signal; and a pre-emphasis driver configured to perform pre-emphasis on the first differential transmission signal and the second differential transmission signal to different amplification degrees in a first mode and a second mode by the pre-emphasis control signals.

    DISPLAY DRIVING DEVICE AND DISPLAY DEVICE INCLUDING THE SAME
    4.
    发明申请
    DISPLAY DRIVING DEVICE AND DISPLAY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20210193004A1

    公开(公告)日：2021-06-24

    申请号：US16925299

    申请日：2020-07-09

    Applicant: Silicon Works Co., Ltd.

    Inventor： Myung Yu Kim ,  Do Seok Kim ,  Hyun Pyo Cho ,  Yong Hwan Moon

    IPC: G09G3/20

    Abstract: The present disclosure discloses a display driving device and a display device including the same, allowing high-speed data communication to be supported by controlling the length of a data packet. The display device may include a timing controller configured to transmit a communication signal, and a source driver connected to the timing controller through a communication link and configured to receive the communication signal. The source driver may receive the communication signal having a format of preamble data, start data, configuration data, end data, and configuration completion data from the timing controller in a configuration mode, and the configuration data may include a header defining a length of a data packet.

    Stream clock generator and embedded DisplayPort system including the same
    5.
    发明授权
    Stream clock generator and embedded DisplayPort system including the same 有权

    公开(公告)号：US11294418B2

    公开(公告)日：2022-04-05

    申请号：US17070091

    申请日：2020-10-14

    Applicant: Silicon Works Co., Ltd.

    Inventor： Yong Hwan Moon ,  Tae Ho Kim ,  Jeong Ho Park

    IPC: G06F1/08 ,  G06F1/10 ,  G06F1/12

    Abstract: Provided are an apparatus capable of generating a stream clock having the same frequency as a frequency in a normal mode, in a panel self-refresh mode and an embedded DisplayPort system including the same. The embedded DisplayPort system includes a stream clock generator. The stream clock generator may include an internal oscillator configured to oscillate an internal clock, a frequency regulator configured to compare frequencies of the internal clock and a link symbol clock, generate control signals, and adjust a frequency of the internal clock using the control signals, wherein the link symbol clock is reconstructed from stream data of the embedded DisplayPort system, and a phase-locked loop configured to generate a stream clock using the internal clock and lock a phase of the stream clock to a phase of the internal clock.

    Display driving device and display device including the same
    6.
    发明授权
    Display driving device and display device including the same 有权

    公开(公告)号：US11127327B2

    公开(公告)日：2021-09-21

    申请号：US16925292

    申请日：2020-07-09

    Applicant: Silicon Works Co., Ltd.

    Inventor： Myung Yu Kim ,  Do Seok Kim ,  Hyun Pyo Cho ,  Yong Hwan Moon

    IPC: G09G3/20

    Abstract: The present disclosure discloses a display driving device and a display device including the same, which are capable of restoring a communication abnormal state to a normal state when a communication abnormality occurs due to an unexpected variable during communication between a timing controller and a plurality of source drivers. The display device may include a timing controller configured to transmit a communication signal, a first source driver connected to the timing controller through a first communication link and configured to receive the communication signal, and a second source driver connected to the timing controller through a second communication link and configured to receive the communication signal. The first source driver and the second source driver may receive a restore command from the timing controller in a communication abnormal state and perform a configuration mode, in which options for restoring a communication state are set, according to configuration data received after the restore command.

    STREAM CLOCK GENERATOR AND EMBEDDED DISPLAYPORT SYSTEM INCLUDING THE SAME
    8.
    发明申请
    STREAM CLOCK GENERATOR AND EMBEDDED DISPLAYPORT SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20210109561A1

    公开(公告)日：2021-04-15

    申请号：US17070091

    申请日：2020-10-14

    Applicant: Silicon Works Co., Ltd.

    Inventor： Yong Hwan Moon ,  Tae Ho Kim ,  Jeong Ho Park

    IPC: G06F1/08 ,  G06F1/12 ,  G06F1/10

    Abstract: Provided are an apparatus capable of generating a stream clock having the same frequency as a frequency in a normal mode, in a panel self-refresh mode and an embedded DisplayPort system including the same. The embedded DisplayPort system includes a stream clock generator. The stream clock generator may include an internal oscillator configured to oscillate an internal clock, a frequency regulator configured to compare frequencies of the internal clock and a link symbol clock, generate control signals, and adjust a frequency of the internal clock using the control signals, wherein the link symbol clock is reconstructed from stream data of the embedded DisplayPort system, and a phase-locked loop configured to generate a stream clock using the internal clock and lock a phase of the stream clock to a phase of the internal clock.

    Circuit for controlling variation in frequency of clock signal
    10.
    发明授权
    Circuit for controlling variation in frequency of clock signal 有权
    用于控制时钟信号频率变化的电路

    公开(公告)号：US09035683B2

    公开(公告)日：2015-05-19

    申请号：US14143401

    申请日：2013-12-30

    Applicant: SILICON WORKS CO., LTD.

    Inventor： Hong Jun Yang ,  Yong Hwan Moon ,  Sang Ho Kim

    IPC: H03L7/06 ,  H03L7/085

    CPC classification number: H03L7/085 ,  H03L7/095 ,  H03L7/1077

    Abstract: Disclosed herein is a circuit for controlling a variation in the frequency of a clock signal for blocking an unwanted variation in the frequency of the clock signal. When a frequency variation out of a set range is generated in a reference clock signal in the state in which the phases of the reference clock signal and a feedback clock signal have been locked, a control voltage for generating the feedback clock signal remains constant so that an abrupt variation generated in the frequency of the feedback clock signal is blocked.

    Abstract translation: 这里公开了一种用于控制时钟信号的频率变化以阻止时钟信号的频率的不期望的变化的电路。 当在参考时钟信号和反馈时钟信号的相位被锁定的状态下在基准时钟信号中产生设定范围之外的频率变化时，用于产生反馈时钟信号的控制电压保持恒定，使得 在反馈时钟信号的频率中产生的突然变化被阻止。

Patent Agency Ranking