公开(公告)号：US6072905A

公开(公告)日：2000-06-06

申请号：US25924

申请日：1998-02-19

申请人： Silvio Cucchi ,  Fabio Valente

发明人： Silvio Cucchi ,  Fabio Valente

IPC分类号： H04N11/04 ,  G06T7/20 ,  H04N7/26 ,  H04N7/32 ,  G06K9/36

CPC分类号： G06T7/2026 ,  H04N19/53 ,  G06T2207/10016

摘要： A method is described for estimating the motion for image sequences carrying out a decimation of the function used for the extraction of the characteristic parameters of an image block. The method is iterated by decreasing the function decimation and carrying out the block-matching on a set of the best matchings of the preceding steps. The method does not require the recalculation of the parameters on the reference image for each block to be matched; moreover, in the extraction of the characteristic parameters of a block, the use of the Integral Projections is not mandatory but one of the possible variants only (FIG. 1).

摘要翻译： 描述了一种用于估计执行用于提取图像块的特征参数的函数的抽取的图像序列的运动的方法。 通过减少函数抽取并对前面步骤的最佳匹配集合执行块匹配来迭代该方法。 该方法不需要对要匹配的每个块的参考图像上的参数进行重新计算; 此外，在提取块的特征参数时，积分投影的使用不是强制性的，而是仅可能的变体之一（图1）。

公开(公告)号：US07535897B2

公开(公告)日：2009-05-19

申请号：US11561401

申请日：2006-11-19

申请人： Georg Post ,  Ludovic Noirie ,  Silvio Cucchi ,  Fabio Valente

发明人： Georg Post ,  Ludovic Noirie ,  Silvio Cucchi ,  Fabio Valente

IPC分类号： H04L12/54

CPC分类号： H04L49/254 ,  H04L49/101 ,  H04L49/205 ,  H04L49/25 ,  H04L49/3045 ,  H04L49/3072 ,  H04L49/503

摘要： In order to switch selectively via a packets switching matrix waiting in the input modules (IMi) to address output modules, an arbitration function (CSC) selects by successive cycles, from all the pairs of input and output modules, separate subsets. Each cycle comprises p successive phases (x) associated respectively to p arbitration functions. Processing units (PUi) each execute the p functions, each function acting on three parameters termed “residual required quantity”, “input capacity” and “output capacity”, the values of which are related to a single pair and are set at the start of the cycle. Each phase consists of N successive steps (y) associated respectively to said subsets, each step being executed in parallel by the processing units (PUi) in order to calculate by means of the arbitration functions the “partial” accepted quantity values and to reset the parameters for the next step. Application to telecommunication networks, particularly multiservice.

摘要翻译： 为了通过在输入模块（IMi）中等待的分组交换矩阵选择性地切换到寻址输出模块，仲裁功能（CSC）从所有输入和输出模块对分别的子集中连续循环选择。 每个周期包括分别与p仲裁功能相关联的p个连续阶段（x）。 处理单元（PUi）每个执行p功能，每个功能作用于称为“剩余所需数量”，“输入容量”和“输出容量”的三个参数，其值与单对相关，并设置在开始 的循环。 每个阶段由分别与所述子集相关联的N个连续步骤（y）组成，每个步骤由处理单元（PUi）并行执行，以便通过仲裁功能计算“部分”接受的数量值并将 下一步的参数。 应用于电信网络，特别是多业务。

公开(公告)号：US20070115957A1

公开(公告)日：2007-05-24

申请号：US11529417

申请日：2006-09-29

申请人： Ludovic Noirie ,  Georg Post ,  Silvio Cucchi ,  Fabio Valente

发明人： Ludovic Noirie ,  Georg Post ,  Silvio Cucchi ,  Fabio Valente

IPC分类号： H04L12/50

CPC分类号： H04L49/254 ,  H04L49/101 ,  H04L49/30

摘要： To selectively route stand-by packets in input modules (IMi) to destination output modules (OMj) via a switching matrix (1), distributed arbitration functions are executable by successive arbitration cycles. Each cycle comprises: a first phase executable by each input controller (ICi) to send each output controller (OCj) requests representative of the quantities of “required” stand-by packets, a second phase executable by each output controller (OCj) to determine the quantity of “admissible” packets depending on the requests. a third phase executable by a central arbitration unit (CSC) to determine “allowed aggregate” quantities depending on all the admissible quantities. a fourth phase executable by each input controller (ICi) to determine the allowed packet quantities depending on the admissible quantities and of the allowed aggregate quantities.

摘要翻译： 为了通过交换矩阵（1）选择性地将输入模块（IMi）中的待机分组路由到目的地输出模块（OMj），分布式仲裁功能可以通过连续的仲裁周期执行。 每个周期包括：由每个输入控制器（ICi）执行以发送代表“所需”待机分组的量的每个输出控制器（OCj））的请求的第一阶段，由每个输出控制器（OCj）执行的第二阶段，以确定 “允许”数据包的数量取决于请求。 第三阶段可由中央仲裁单位（CSC）执行，以根据所有允许的数量确定“允许的总体”数量。 可由每个输入控制器（ICi）执行的第四阶段，以根据容许量和允许的总量来确定允许的分组数量。

公开(公告)号：US07639679B2

公开(公告)日：2009-12-29

申请号：US11529417

申请日：2006-09-29

申请人： Ludovic Noirie ,  Georg Post ,  Silvio Cucchi ,  Fabio Valente

发明人： Ludovic Noirie ,  Georg Post ,  Silvio Cucchi ,  Fabio Valente

IPC分类号： H04L12/50

CPC分类号： H04L49/254 ,  H04L49/101 ,  H04L49/30

摘要： To selectively route stand-by packets in input modules to destination output modules via a switching matrix, distributed arbitration functions are executable by successive arbitration cycles. Each cycle comprises: a first phase executable by each input controller to send each output controller requests representative of the quantities of required stand-by packets; a second phase executable by each output controller to determine the quantity of admissible packets depending on the requests; a third phase executable by a central arbitration unit to determine allowed aggregate quantities depending on all the admissible quantities; and a fourth phase executable by each input controller to determine the allowed packet quantities depending on the admissible quantities and of the allowed aggregate quantities.

摘要翻译： 为了通过切换矩阵选择性地将输入模块中的备用分组路由到目标输出模块，分布式仲裁功能可以通过连续的仲裁周期执行。 每个周期包括：由每个输入控制器执行的第一阶段，以发送每个输出控制器请求代表所需待机数量的数量; 第二阶段，可由每个输出控制器执行以根据请求确定可接受分组的数量; 第三阶段可由中央仲裁单位执行，以根据所有允许的数量确定允许的总量; 以及由每个输入控制器执行的第四阶段，以根据允许的量和允许的总量来确定允许的分组数量。

公开(公告)号：US20070127514A1

公开(公告)日：2007-06-07

申请号：US11561401

申请日：2006-11-19

申请人： Georg POST ,  Ludovic Noirie ,  Silvio Cucchi ,  Fabio Valente

发明人： Georg POST ,  Ludovic Noirie ,  Silvio Cucchi ,  Fabio Valente

IPC分类号： H04L12/56 ,  H04L12/50

CPC分类号： H04L49/254 ,  H04L49/101 ,  H04L49/205 ,  H04L49/25 ,  H04L49/3045 ,  H04L49/3072 ,  H04L49/503

摘要： In order to switch selectively via a packets switching matrix waiting in the input modules (IMi) to address output modules, an arbitration function (CSC) selects by successive cycles, from all the pairs of input and output modules, separate subsets. Each cycle comprises p successive phases (x) associated respectively to p arbitration functions. Processing units (PUi) each execute the p functions, each function acting on three parameters termed “residual required quantity”, “input capacity” and “output capacity”, the values of which are related to a single pair and are set at the start of the cycle. Each phase consists of N successive steps (y) associated respectively to said subsets, each step being executed in parallel by the processing units (PUi) in order to calculate by means of the arbitration functions the “partial” accepted quantity values and to reset the parameters for the next step. Application to telecommunication networks, particularly multiservice.

摘要翻译： 为了通过在输入模块（IMi）中等待的分组交换矩阵选择性地切换到寻址输出模块，仲裁功能（CSC）从所有输入和输出模块对分别的子集中连续循环选择。 每个周期包括分别与p仲裁功能相关联的p个连续阶段（x）。 处理单元（PUi）每个执行p功能，每个功能作用于称为“剩余所需数量”，“输入容量”和“输出容量”的三个参数，其值与单对相关，并设置在开始 的循环。 每个阶段由分别与所述子集相关联的N个连续步骤（y）组成，每个步骤由处理单元（PUi）并行执行，以便通过仲裁功能计算“部分”接受的数量值并将 下一步的参数。 应用于电信网络，特别是多业务。

公开(公告)号：US08429511B2

公开(公告)日：2013-04-23

申请号：US12592140

申请日：2009-11-18

申请人： Silvio Cucchi ,  Giuseppe Badalucco ,  Carlo Costantini ,  Riccardo Gemelli ,  Luigi Ronchetti

发明人： Silvio Cucchi ,  Giuseppe Badalucco ,  Carlo Costantini ,  Riccardo Gemelli ,  Luigi Ronchetti

IPC分类号： G06F11/00

CPC分类号： H04Q3/68 ,  H04L49/101 ,  H04L49/552 ,  H04Q3/54558

摘要： Equipment protection of a switch matrix (SM) in a network node, which contains a number of matrix modules (M1.1-M4.4, E1.5-E4.6) is achieved by slicing an input signal into k parallel signal slices (x(0)-x(3)) with k>2; coding the k signal slices into a number of n coded signal slices (x(0)-x(5)) with n>k+1 using an error correcting code to add redundancy to said input signal; switching said n coded signal slices through the switching matrix (SM) via n distinct matrix modules; and decoding the n coded signal slices into k decoded signal slices to correct errors introduced while passing through said switch matrix. Preferably, the switch matrix (SM) contains a first number of matrix boards (MB1-MB4, EB5, EB6), each carrying a second number of matrix modules (M1.1-M4.4, E1.5-E4.6). The n coded signal slices are switched via matrix modules on n distinct matrix boards.

摘要翻译： 通过将输入信号分割成k个并行信号片段来实现包含多个矩阵模块（M1.1-M4.4，E1.5-E4.6）的网络节点中的开关矩阵（SM）的设备保护 （x（0）-x（3）），k> 2; 使用纠错码将k个信号片段编码为具有n> k + 1的n个编码信号片（x（0）-x（5））的数量，以向所述输入信号添加冗余; 通过开关矩阵（SM）通过n个不同的矩阵模块切换所述n个编码信号片; 以及将所述n个编码信号片段解码为k个解码信号片，以校正通过所述开关矩阵时引入的错误。 优选地，开关矩阵（SM）包含第一数量的矩阵板（MB1-MB4，EB5，EB6），每个矩阵板承载第二数量的矩阵模块（M1.1-M4.4，E1.5-E4.6） 。 通过n个不同矩阵板上的矩阵模块切换n个编码信号片。

公开(公告)号：US07917797B2

公开(公告)日：2011-03-29

申请号：US12125270

申请日：2008-05-22

申请人： Paolo Novellini ,  Silvio Cucchi ,  Giovanni Guasti

发明人： Paolo Novellini ,  Silvio Cucchi ,  Giovanni Guasti

IPC分类号： G06F1/08

CPC分类号： H03L7/1806 ,  H03L7/091 ,  H03L7/0994 ,  H03L2207/50 ,  H04J3/0691

摘要： Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors.

摘要翻译： 提供了从输入信号产生具有减小的偏移的一个或多个输出时钟信号的电路。 输入信号具有从具有与输出时钟信号的频率不同的频率的原始时钟信号的转变导出的转变。 输出时钟信号的频率是乘以输入信号的频率和整数比。 该电路包括一个累加器，一个分数相位检测器和一个环路滤波器。 累加器周期性地将数字偏移值添加到数值相位值。 从该数值相位值产生输出时钟信号。 分数相位检测器从数字相位值生成输入信号的每个转换的相应数值相位误差。 环路滤波器从相应的数值相位误差的滤波中产生数字偏移值。

公开(公告)号：US07720111B2

公开(公告)日：2010-05-18

申请号：US10710090

申请日：2004-06-17

申请人： Alberto Bellato ,  Silvio Cucchi ,  Silvano Frigerio ,  Alberto Lometti ,  Luca Razzetti ,  Stefano Gastaldello

发明人： Alberto Bellato ,  Silvio Cucchi ,  Silvano Frigerio ,  Alberto Lometti ,  Luca Razzetti ,  Stefano Gastaldello

IPC分类号： H04J3/00

CPC分类号： H04J3/1611

摘要： The present invention provides for a method and apparatus for carrying out connection and related input/output processing functions in a Sinchronous Digital Hierarchy (SDH/SONET) transport node (network), in which the payload switching matrices (e.g. MSPC and HPC matrices for an High Order VC system) collapse into one single functional block (MTRX), while the Virtual Container (VCs) monitoring functions (HVC_RX, HVC_TX) are shifted to the Input/Output position of the matrices.

摘要翻译： 本发明提供了一种用于在正时数字体系（SDH / SONET）传输节点（网络）中执行连接和相关输入/输出处理功能的方法和装置，其中有效载荷切换矩阵（例如，MSPC和HPC矩阵 高阶VC系统）折叠成单个功能块（MTRX），而虚拟容器（VC）监视功能（HVC_RX，HVC_TX）被移动到矩阵的输入/输出位置。

公开(公告)号：US20090289667A1

公开(公告)日：2009-11-26

申请号：US12125270

申请日：2008-05-22

申请人： Paolo Novellini ,  Silvio Cucchi ,  Giovanni Guasti

发明人： Paolo Novellini ,  Silvio Cucchi ,  Giovanni Guasti

IPC分类号： H03B21/00 ,  H03L7/06

CPC分类号： H03L7/1806 ,  H03L7/091 ,  H03L7/0994 ,  H03L2207/50 ,  H04J3/0691

摘要： Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors.

摘要翻译： 提供了从输入信号产生具有减小的偏移的一个或多个输出时钟信号的电路。 输入信号具有从具有与输出时钟信号的频率不同的频率的原始时钟信号的转变导出的转变。 输出时钟信号的频率是乘以输入信号的频率和整数比。 该电路包括一个累加器，一个分数相位检测器和一个环路滤波器。 累加器周期性地将数字偏移值添加到数值相位值。 从该数值相位值产生输出时钟信号。 分数相位检测器从数字相位值生成输入信号的每个转换的相应数值相位误差。 环路滤波器从相应的数值相位误差的滤波中产生数字偏移值。

公开(公告)号：US20050204254A1

公开(公告)日：2005-09-15

申请号：US11012302

申请日：2004-12-16

申请人： Silvio Cucchi ,  Sonia Rinaldi ,  Marco Andreasi

发明人： Silvio Cucchi ,  Sonia Rinaldi ,  Marco Andreasi

IPC分类号： H03M13/29 ,  H03M13/00

CPC分类号： H03M13/2948 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/293

摘要： Disclosed is a method and erasure FEC decoder for correcting a pattern of errors by a two-dimensional decoding, the pattern of errors comprising at least two codewords in both a first and a second dimensions with a number of errors in common higher than the capacity of the code which is used for decoding. The method comprises the steps of: performing a full capacity decoding along the second dimension for removing possible false corrections introduced by a previous decoding performed along the first dimension; performing a reduced-capacity decoding along the first dimension, for identifying errored codewords along the first dimension; performing a full capacity decoding along the second dimension with disabled correction feature for identifying errored codewords along the second dimension; detecting the error coordinates from the information from steps b) and c); and correcting the detected pattern of errors.

摘要翻译： 公开了一种用于通过二维解码来校正错误模式的方法和擦除FEC解码器，错误模式包括在第一和第二维度中的至少两个码字，其中多个错误共同高于 用于解码的代码。 该方法包括以下步骤：沿着第二维执行全容量解码，以去除沿着第一维度执行的先前解码引入的可能的伪校正; 沿着第一维度执行简化容量解码，用于识别沿着第一维度的错误码字; 沿着所述第二维度执行具有禁用校正特征的全容量解码，用于识别沿着所述第二维度的错误码字; 根据来自步骤b）和c）的信息检测误差坐标; 并校正检测到的错误模式。