公开(公告)号：US20200042029A1

公开(公告)日：2020-02-06

申请号：US16600123

申请日：2019-10-11

Applicant: SOCIONEXT INC.

Inventor： Kyota SHIMIZU ,  Toshiya SUZUKI ,  Tomohiko KOTO

IPC: G05F1/618 ,  H03K19/00 ,  H03K19/0175 ,  H03K3/356 ,  H03K19/003 ,  G11C7/10 ,  H03K3/281

Abstract: An output circuit includes: a first p-type transistor having a source connected to VDDH and a gate to which an input signal is fed; and a second p-type transistor having a source connected to the drain of the first p-type transistor, a drain connected to an output terminal, and a gate connected to a first node. A capacitor has one terminal to which the input signal is fed and the other terminal connected to the first node. A first n-type transistor has a source connected to VDDL, a drain connected to the first node, and a gate to which a signal corresponding to the input signal is fed. A second n-type transistor has a source and a gate both connected to VDDL and a drain connected to the first node.

公开(公告)号：US20210013881A1

公开(公告)日：2021-01-14

申请号：US16998330

申请日：2020-08-20

Applicant: SOCIONEXT INC.

Inventor： Toshiya SUZUKI ,  Tomohiko KOTO

IPC: H03K17/687 ,  H03K5/13 ,  H03K19/0175

Abstract: A drive assist circuit includes a pulse generation circuit which outputs a pulse to control an assist operation when an assist signal makes a first transition corresponding to a transition of a gate signal from a high level to a low level. The pulse generation circuit includes a delay circuit provided in one of two inputs of a logic gate. The delay circuit is configured such that a delay is greater when an input makes a transition corresponding to the first transition of the assist signal, as compared to a case where the input makes a transition corresponding to an inverse of the first transition.

公开(公告)号：US20240250676A1

公开(公告)日：2024-07-25

申请号：US18627023

申请日：2024-04-04

Applicant: Socionext Inc.

Inventor： Kyota SHIMIZU ,  Tomohiko KOTO ,  Masahisa IIDA

IPC: H03K17/041 ,  H03K19/0185

CPC classification number: H03K17/04106 ,  H03K19/018507

Abstract: An output circuit outputs an output signal having an amplitude VCCH responsive to an input signal having an amplitude VCCL. The output circuit includes: first and second p-type transistors connected in series between VCCH and an output terminal; a first n-type transistor grounded at its source and receiving a first signal at its gate; a third p-type transistor connected to VCCH at its source, connected to the gate of the first p-type transistor at its drain, and receiving a second signal at its gate; and a first diode connected between the drains of the first n-type transistor and the third p-type transistor.

公开(公告)号：US20170012612A1

公开(公告)日：2017-01-12

申请号：US15173293

申请日：2016-06-03

Applicant: SOCIONEXT INC.

Inventor： Tomohiko KOTO ,  Kenichi Konishi ,  Osamu Uno

IPC: H03K3/356

CPC classification number: H03K3/356086 ,  H03K3/35613 ,  H03K3/356165 ,  H03K3/356182

Abstract: A level conversion circuit includes: first P-ch and N-ch transistors and second P-ch and N-ch transistors respectively connected in series between first and second power sources; third and fourth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and the drain of the first and second P-ch transistors; and fifth and sixth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and a third power source, wherein differential input signals are applied to the gates of the first and second N-ch transistors, a bias voltage is applied to the gates of the third and fourth P-ch transistors, the gate of the fifth and sixth P-ch transistors are respectively connected to connection nodes of the first P-ch and N-ch transistors the second P-ch and N-ch transistors.

Abstract translation: 电平转换电路包括：分别串联连接在第一和第二电源之间的第一P-ch和N-ch晶体管和第二P-ch和N-ch晶体管; 分别连接在第二和第一P-ch晶体管的栅极和第一和第二P-ch晶体管的漏极之间的第三和第四Pch晶体管; 以及分别连接在第二和第一P-ch晶体管的栅极和第三电源之间的第五和第六Pch晶体管，其中差分输入信号施加到第一和第二N沟道晶体管的栅极，偏置电压 施加到第三和第四P-ch晶体管的栅极，第五和第六Pch晶体管的栅极分别连接到第一P-ch和N-ch晶体管的连接节点，第二P-ch和N -ch晶体管。