公开(公告)号：US09755574B2

公开(公告)日：2017-09-05

申请号：US15222421

申请日：2016-07-28

Applicant: SONY CORPORATION

Inventor： Jeremy Chatwin

IPC: H03K3/03 ,  H03B1/04 ,  H03L7/24 ,  H03K3/356

CPC classification number: H03B1/04 ,  H03B2200/009 ,  H03K3/013 ,  H03K3/0315 ,  H03K3/0322 ,  H03K3/356121 ,  H03L7/24

Abstract: Various aspects of an injection-locked oscillator and method for controlling jitter and/or phase noise are disclosed herein. In accordance with an embodiment, an injection-locked oscillator includes one or more circuits that are configured to receive a pair of complementary phase output signals from one or more gain stages of the injection-locked oscillator. The one or more circuits may be configured to receive one or more switching signals. The received pair of complementary phase output signals are shorted by use of the one or more received switching signals. The shorting reduces the phase difference between an input signal and an output signal of the injection-locked oscillator.

公开(公告)号：US10402166B2

公开(公告)日：2019-09-03

申请号：US15017330

申请日：2016-02-05

Applicant: SONY CORPORATION

Inventor： Jeremy Chatwin ,  Jacob Adams Wysocki

IPC: G06F7/504 ,  G06F7/509 ,  G06F7/523

Abstract: Various aspects of a system and method to process data in an adder based circuit, such as an integrated circuit, are disclosed herein. In accordance with an embodiment, a first addend is encoded as a first unary number. The first unary number comprises a token bit. A second addend is encoded as a second unary number. A first shift operation is performed on the token bit in the first unary number based on the second unary number. The first shift operation is performed to generate an output unary number. The generated output unary number is decoded to a number representation that corresponds to the number representation of the first addend and/or the second addend. The decoded number representation indicates a summation of the first addend and the second addend.

公开(公告)号：US09350527B1

公开(公告)日：2016-05-24

申请号：US14666528

申请日：2015-03-24

Applicant: Sony Corporation

Inventor： Takashi Masuda ,  Yosuke Ueno ,  Zhiwei Zhou ,  Kenichi Maruko ,  Jeremy Chatwin

IPC: H04L7/00

CPC classification number: H04L7/033 ,  H03L7/0807 ,  H03L7/0812 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0995 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0276

Abstract: There is provided a reception unit, including: a transition detection section configured to detect a transition of an input data signal; an oscillation section configured to generate a clock signal and vary a phase of the clock signal based on a result of detection made by the transition detection section, the clock signal having a frequency in accordance with a first control signal; a first sampling section configured to sample the input data signal based on the clock signal and thereby generate an output data signal; and a control section configured to generate the first control signal based on the input data signal, the output data signal, and the clock signal.

Abstract translation: 提供了一种接收单元，包括：转换检测部分，被配置为检测输入数据信号的转换; 振荡部，被配置为产生时钟信号，并且基于由所述转移检测部进行的检测结果来改变所述时钟信号的相位，所述时钟信号具有根据第一控制信号的频率; 第一采样部，被配置为基于所述时钟信号对所述输入数据信号进行采样，从而生成输出数据信号; 以及控制部，被配置为基于所述输入数据信号，所述输出数据信号和所述时钟信号来生成所述第一控制信号。