公开(公告)号：US08970312B2

公开(公告)日：2015-03-03

申请号：US13959015

申请日：2013-08-05

Applicant: Sony Corporation

Inventor： Kenichi Maruko ,  Masayuki Katakura

IPC: H03K3/03 ,  H03L7/00 ,  H03L3/00

CPC classification number: H03L7/00 ,  H03K3/014 ,  H03K3/0322 ,  H03L3/00

Abstract: There is provided a differential ring oscillation circuit including a differential ring oscillation unit in which delay circuits, to which signals of 2 phases are input, and which delay and output the input signals of 2 phases, are connected at even stages in a ring form, first and second common-mode level detection units that detect that the input signals of 2 phases of one delay circuit at an even stage of the differential ring oscillation unit and the input signals of 2 phases of one delay circuit at an odd stage of the differential ring oscillation unit are at same predetermined levels, respectively, and first and second switches that set, to specific potentials, one of the output signals of 2 phases of the delay circuit delaying the input signals of 2 phases, when the first and second common-mode level detection units detect the same predetermined levels, respectively.

Abstract translation: 提供了一种差动环振荡电路，其包括差动环振荡单元，其中输入两相信号的延迟电路，并且延迟和输出两相输入信号以环形的顺序连接， 第一和第二共模电平检测单元，其检测差分环形振荡单元的偶数阶段的一个延迟电路的2相的输入信号和差分奇数级的一个延迟电路的2相的输入信号 环形振荡单元分别处于相同的预定电平;以及第一和第二开关，其将特征电位设置为延迟电路的2相的输出信号中的一个延迟2相的输入信号， 模式电平检测单元分别检测相同的预定电平。

公开(公告)号：US10177878B2

公开(公告)日：2019-01-08

申请号：US15404381

申请日：2017-01-12

Applicant: SONY CORPORATION

Inventor： Kazuhisa Funamoto ,  Tatsuo Shinbashi ,  Tatsuya Sugioka ,  Kenichi Maruko ,  Naohiro Koshisaka ,  Hiroo Takahashi

IPC: H03M5/14 ,  H04L1/00 ,  H04L25/49 ,  H04N17/00 ,  H04N5/378

Abstract: There is provided an information processing device including an acquirer that acquires second data obtained by converting first data constituted by bit data having a first number of bits into symbols having a second number of bits greater than the first number of bits, with respect to each of the bit data, a comparator that compares a first symbol string constituted by a plurality of symbols contained in the second data prior to reverse conversion of the acquired second data into the first data, to a second symbol string representing a code targeted for detection, and a detector that detects the first symbol string as the code targeted for detection from the second data, on the basis of the result of the comparison by the comparator.

公开(公告)号：US09407480B2

公开(公告)日：2016-08-02

申请号：US14626171

申请日：2015-02-19

Applicant: Sony Corporation

Inventor： Takashi Yokokawa ,  Kenichi Maruko

IPC: H04L7/00 ,  H04L27/01 ,  H04L25/14 ,  H04L7/033 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089

CPC classification number: H04L27/01 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/0898 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/14 ,  Y10T307/766

Abstract: An apparatus according to an embodiment of the present disclosure includes a plurality of target circuits, the number of the target circuits being more than a required number of the target circuits; a characteristic adjustment unit configured to adjust characteristics of the target circuits; and a control unit configured to control a state of the target circuits between a used state and an unused state. The control unit controls the required number of the target circuits to be in the used state and controls the rest of the target circuits to be in the unused state. The characteristic adjustment unit adjusts the characteristics with respect to the target circuits in the unused state.

Abstract translation: 根据本公开的实施例的装置包括多个目标电路，目标电路的数量大于目标电路的所需数量; 特征调整单元，被配置为调整目标电路的特性; 以及控制单元，被配置为控制目标电路在使用状态和未使用状态之间的状态。 控制单元控制目标电路的所需数量处于使用状态，并将目标电路的其余部分控制在未使用状态。 特征调整单元在未使用状态下调整相对于目标电路的特性。

公开(公告)号：US09350527B1

公开(公告)日：2016-05-24

申请号：US14666528

申请日：2015-03-24

Applicant: Sony Corporation

Inventor： Takashi Masuda ,  Yosuke Ueno ,  Zhiwei Zhou ,  Kenichi Maruko ,  Jeremy Chatwin

IPC: H04L7/00

CPC classification number: H04L7/033 ,  H03L7/0807 ,  H03L7/0812 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0995 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0276

Abstract: There is provided a reception unit, including: a transition detection section configured to detect a transition of an input data signal; an oscillation section configured to generate a clock signal and vary a phase of the clock signal based on a result of detection made by the transition detection section, the clock signal having a frequency in accordance with a first control signal; a first sampling section configured to sample the input data signal based on the clock signal and thereby generate an output data signal; and a control section configured to generate the first control signal based on the input data signal, the output data signal, and the clock signal.

Abstract translation: 提供了一种接收单元，包括：转换检测部分，被配置为检测输入数据信号的转换; 振荡部，被配置为产生时钟信号，并且基于由所述转移检测部进行的检测结果来改变所述时钟信号的相位，所述时钟信号具有根据第一控制信号的频率; 第一采样部，被配置为基于所述时钟信号对所述输入数据信号进行采样，从而生成输出数据信号; 以及控制部，被配置为基于所述输入数据信号，所述输出数据信号和所述时钟信号来生成所述第一控制信号。

公开(公告)号：US09065607B2

公开(公告)日：2015-06-23

申请号：US14084960

申请日：2013-11-20

Applicant: Sony Corporation

Inventor： Kenichi Maruko ,  Yosuke Ueno

IPC: H03D3/24 ,  H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0037 ,  H04L7/0041 ,  H04L7/0337

Abstract: A clock data recovery circuit includes: an oscillator that outputs a clock signal; a phase comparator that outputs a signal corresponding to a phase difference between an input reception data signal and the clock signal; a divider that outputs a feedback clock signal; a first variable delay circuit that outputs a delay data signal; a second variable delay circuit that outputs a delay feedback clock signal; a frequency phase comparator that outputs a signal corresponding to a frequency difference and a phase difference between the delay data signal and the delay feedback clock signal; a lock detector that outputs a determination signal indicating whether or not the frequency difference and the phase difference are within a predetermined range; and a multiplexer that receives the determination signal and select a signal of the phase comparator and a signal of the frequency phase comparator.

Abstract translation: 时钟数据恢复电路包括：输出时钟信号的振荡器; 相位比较器，输出与输入的接收数据信号和时钟信号之间的相位差对应的信号; 输出反馈时钟信号的分频器; 输出延迟数据信号的第一可变延迟电路; 输出延迟反馈时钟信号的第二可变延迟电路; 频率相位比较器，输出对应于延迟数据信号和延迟反馈时钟信号之间的频率差和相位差的信号; 锁定检测器，其输出指示频率差和相位差是否在预定范围内的确定信号; 以及多路复用器，其接收所述确定信号并选择所述相位比较器的信号和所述频率相位比较器的信号。

公开(公告)号：US09054689B2

公开(公告)日：2015-06-09

申请号：US14156770

申请日：2014-01-16

Applicant: Sony Corporation

Inventor： Kenichi Maruko

IPC: H03L7/085 ,  H03K3/3562

CPC classification number: H03K3/35625 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/095

Abstract: A phase comparison circuit includes: a first flip-flop configured to receive a data signal and a clock signal; a second flip-flop configured to receive an output signal of the first flip-flop and a signal that is an inversion of logic of the clock signal; a delay circuit configured to give delay time to the data signal, in which the delay time is equal to or longer than signal delay time from a clock terminal of the first flip-flop to a Q output terminal of the first flip-flop; a first exclusive OR circuit configured to receive an output signal of the delay circuit and the output signal of the first flip-flop; and a second exclusive OR circuit configured to receive the output signal of the first flip-flop and an output signal of the second flip-flop.

Abstract translation: 相位比较电路包括：第一触发器，被配置为接收数据信号和时钟信号; 第二触发器，被配置为接收第一触发器的输出信号和作为时钟信号的逻辑反转的信号; 延迟电路，被配置为向所述数据信号提供延迟时间，其中所述延迟时间等于或大于从所述第一触发器的时钟端子到所述第一触发器的Q输出端子的信号延迟时间; 第一异或电路，被配置为接收延迟电路的输出信号和第一触发器的输出信号; 以及第二异或电路，被配置为接收第一触发器的输出信号和第二触发器的输出信号。

公开(公告)号：US20140300755A1

公开(公告)日：2014-10-09

申请号：US14353912

申请日：2012-11-30

Applicant: SONY CORPORATION

Inventor： Kazuhisa Funamoto ,  Tatsuo Shinbashi ,  Tatsuya Sugioka ,  Kenichi Maruko ,  Naohiro Koshisaka ,  Hiroo Takahashi

IPC: H04N17/00 ,  H04N5/378

CPC classification number: H04L1/0072 ,  H03M5/145 ,  H04L1/0045 ,  H04L1/0057 ,  H04L25/4908 ,  H04N5/378 ,  H04N17/002

Abstract: There is provided an information processing device including an acquirer that acquires second data obtained by converting first data constituted by bit data having a first number of bits into symbols having a second number of bits greater than the first number of bits, with respect to each of the bit data, a comparator that compares a first symbol string constituted by a plurality of symbols contained in the second data prior to reverse conversion of the acquired second data into the first data, to a second symbol string representing a code targeted for detection, and a detector that detects the first symbol string as the code targeted for detection from the second data, on the basis of the result of the comparison by the comparator.

Abstract translation: 提供了一种信息处理装置，包括：获取单元，其通过将由具有第一比特数的比特数据构成的第一数据转换成具有大于第一比特数的第二比特数的符号，获得的第二数据相对于 所述比特数据，比较器，将在所获取的第二数据逆向转换为第一数据之前将包含在第二数据中的多个符号构成的第一符号串与表示用于检测的代码的第二符号串进行比较，以及 基于比较器的比较结果，从第二数据检测第一符号串作为检测对象的检测器。

公开(公告)号：US09565424B2

公开(公告)日：2017-02-07

申请号：US14353912

申请日：2012-11-30

Applicant: SONY CORPORATION

Inventor： Kazuhisa Funamoto ,  Tatsuo Shinbashi ,  Tatsuya Sugioka ,  Kenichi Maruko ,  Naohiro Koshisaka ,  Hiroo Takahashi

IPC: H04N17/00 ,  H04L1/00 ,  H03M5/14 ,  H04N5/30 ,  H04L25/49 ,  H04N5/378

CPC classification number: H04L1/0072 ,  H03M5/145 ,  H04L1/0045 ,  H04L1/0057 ,  H04L25/4908 ,  H04N5/378 ,  H04N17/002

Abstract: There is provided an information processing device including an acquirer that acquires second data obtained by converting first data constituted by bit data having a first number of bits into symbols having a second number of bits greater than the first number of bits, with respect to each of the bit data, a comparator that compares a first symbol string constituted by a plurality of symbols contained in the second data prior to reverse conversion of the acquired second data into the first data, to a second symbol string representing a code targeted for detection, and a detector that detects the first symbol string as the code targeted for detection from the second data, on the basis of the result of the comparison by the comparator.

Abstract translation: 提供了一种信息处理装置，包括：获取单元，其通过将由具有第一比特数的比特数据构成的第一数据转换成具有大于第一比特数的第二比特数的符号，获得的第二数据相对于 所述比特数据，比较器，将在所获取的第二数据逆向转换为第一数据之前将包含在第二数据中的多个符号构成的第一符号串与表示用于检测的代码的第二符号串进行比较，以及 基于比较器的比较结果，从第二数据检测第一符号串作为检测对象的检测器。

公开(公告)号：US20140203842A1

公开(公告)日：2014-07-24

申请号：US14156770

申请日：2014-01-16

Applicant: Sony Corporation

Inventor： Kenichi Maruko

IPC: H03K3/012

CPC classification number: H03K3/35625 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/095

Abstract: A phase comparison circuit includes: a first flip-flop configured to receive a data signal and a clock signal; a second flip-flop configured to receive an output signal of the first flip-flop and a signal that is an inversion of logic of the clock signal; a delay circuit configured to give delay time to the data signal, in which the delay time is equal to or longer than signal delay time from a clock terminal of the first flip-flop to a Q output terminal of the first flip-flop; a first exclusive OR circuit configured to receive an output signal of the delay circuit and the output signal of the first flip-flop; and a second exclusive OR circuit configured to receive the output signal of the first flip-flop and an output signal of the second flip-flop.

Abstract translation: 相位比较电路包括：第一触发器，被配置为接收数据信号和时钟信号; 第二触发器，被配置为接收第一触发器的输出信号和作为时钟信号的逻辑反转的信号; 延迟电路，被配置为向所述数据信号提供延迟时间，其中所述延迟时间等于或大于从所述第一触发器的时钟端子到所述第一触发器的Q输出端子的信号延迟时间; 第一异或电路，被配置为接收延迟电路的输出信号和第一触发器的输出信号; 以及第二异或电路，被配置为接收第一触发器的输出信号和第二触发器的输出信号。

公开(公告)号：US20140177771A1

公开(公告)日：2014-06-26

申请号：US14084960

申请日：2013-11-20

Applicant: SONY CORPORATION

Inventor： Kenichi Maruko ,  Yosuke Ueno

IPC: H04L7/033

CPC classification number: H04L7/0037 ,  H04L7/0041 ,  H04L7/0337

Abstract: A clock data recovery circuit includes: an oscillator that outputs a clock signal; a phase comparator that outputs a signal corresponding to a phase difference between an input reception data signal and the clock signal; a divider that outputs a feedback clock signal; a first variable delay circuit that outputs a delay data signal; a second variable delay circuit that outputs a delay feedback clock signal; a frequency phase comparator that outputs a signal corresponding to a frequency difference and a phase difference between the delay data signal and the delay feedback clock signal; a lock detector that outputs a determination signal indicating whether or not the frequency difference and the phase difference are within a predetermined range; and a multiplexer that receives the determination signal and select a signal of the phase comparator and a signal of the frequency phase comparator.

Abstract translation: 时钟数据恢复电路包括：输出时钟信号的振荡器; 相位比较器，输出与输入的接收数据信号和时钟信号之间的相位差对应的信号; 输出反馈时钟信号的分频器; 输出延迟数据信号的第一可变延迟电路; 输出延迟反馈时钟信号的第二可变延迟电路; 频率相位比较器，输出对应于延迟数据信号和延迟反馈时钟信号之间的频率差和相位差的信号; 锁定检测器，其输出指示频率差和相位差是否在预定范围内的确定信号; 以及多路复用器，其接收所述确定信号并选择所述相位比较器的信号和所述频率相位比较器的信号。