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    TIMING ADJUSTMENT CIRCUIT, SOLID-STATE IMAGE PICKUP ELEMENT, AND CAMERA SYSTEM
    1.
    发明申请
    TIMING ADJUSTMENT CIRCUIT, SOLID-STATE IMAGE PICKUP ELEMENT, AND CAMERA SYSTEM 有权
    时序调整电路，固态图像拾取元件和摄像机系统

    公开(公告)号：US20130070118A1

    公开(公告)日：2013-03-21

    申请号：US13674555

    申请日：2012-11-12

    Applicant: Sony Corporation

    Inventor： Masahiro Hatano ,  Masaru Kikuchi

    IPC: H01L27/146 ,  H04N5/225

    CPC classification number: H01L27/14609 ,  H03L7/0805 ,  H03L7/0995 ,  H03L7/183 ,  H04L7/0012 ,  H04L7/0041 ,  H04N5/225

    Abstract: A timing adjustment circuit includes at least one data line; a phase synchronization circuit that includes a plurality of oscillation delay elements which oscillate an oscillation signal, and that is configured to oscillate the oscillation signal by synchronizing a phase of a feedback clock with a phase of a reference clock; at least one delay circuit that includes a delay element which is disposed on the data line and which is equivalent to one of the plurality of oscillation delay elements, and that is configured to delay data which is to be transmitted on the data line; and a delay adjustment unit configured to adjust an amount of delay of the delay element of the delay circuit in accordance with a signal associated with oscillation of the phase synchronization circuit.

    Abstract translation: 定时调整电路包括至少一条数据线; 相位同步电路，其包括使振荡信号振荡的多个振荡延迟元件，并且被配置为通过使反馈时钟的相位与参考时钟的相位同步来振荡所述振荡信号; 至少一个延迟电路，其包括设置在所述数据线上并且等效于所述多个振荡延迟元件中的一个的延迟元件，并且被配置为延迟将在所述数据线上发送的数据; 以及延迟调整单元，被配置为根据与相位同步电路的振荡相关联的信号来调整延迟电路的延迟元件的量。

    Solid-state imaging device, imaging device, electronic equipment, A/D converter and A/D conversion method
    3.
    发明授权
    Solid-state imaging device, imaging device, electronic equipment, A/D converter and A/D conversion method 有权
    固态成像装置，成像装置，电子设备，A / D转换器和A / D转换方法

    公开(公告)号：US09077919B2

    公开(公告)日：2015-07-07

    申请号：US14244482

    申请日：2014-04-03

    Applicant: Sony Corporation

    Inventor： Hayato Wakabayashi ,  Masaru Kikuchi ,  Hiroshi Iwasa ,  Yuuki Yamagata

    IPC: H04N5/357 ,  H04N5/335 ,  H03M1/06 ,  H03M1/10 ,  H04N5/378 ,  H03M1/34 ,  H03M1/08 ,  H04N5/3745 ,  H03M1/12 ,  H03M1/56 ,  H03M1/74

    CPC classification number: H04N5/357 ,  H03M1/0658 ,  H03M1/08 ,  H03M1/1023 ,  H03M1/1205 ,  H03M1/123 ,  H03M1/129 ,  H03M1/34 ,  H03M1/56 ,  H03M1/745 ,  H04N5/335 ,  H04N5/37455 ,  H04N5/378

    Abstract: In a reference signal comparison AD conversion scheme, a reference signal SLP_ADC and each of P and D phases of a pixel signal voltage Vx are compared. A count clock CKcnt1 is counted based on the comparison result. The counting result data is converted into signal data Dsig, i.e., the difference between the P and D phases, which is also subjected to CDS. At this time, the n-bit AD conversion is performed on each of the P and D phases of the pixel signal voltage Vx, followed by summation for digital integration. This prevents any possible detrimental effects that may be caused by summation in the analog domain. Although the signal data becomes W times greater, noise will likely become √W times greater. This alleviates the problem of random noise resulting from AD conversion such as quantizing noise and circuit noise that do not exist in the analog domain, thus reducing the noise.

    Abstract translation: 在参考信号比较AD转换方案中，比较参考信号SLP_ADC和像素信号电压Vx的P和D相位中的每一个。 基于比较结果对计数时钟CKcnt1进行计数。 计数结果数据被转换为信号数据Dsig，也就是也经历CDS的P相和D相之间的差。 此时，对像素信号电压Vx的P相和D相进行n位AD转换，然后进行数字积分的求和。 这可以防止可能由模拟域中的相加引起的任何可能的有害影响。 虽然信号数据变为W倍，噪声可能会增加到更多的√W倍。 这减轻了AD转换产生的随机噪声的问题，例如量化噪声和模拟域中不存在的电路噪声，从而降低噪声。

    SOLID-STATE IMAGING DEVICE, IMAGING DEVICE, ELECTRONIC EQUIPMENT, A/D CONVERTER AND A/D CONVERSION METHOD
    4.
    发明申请
    SOLID-STATE IMAGING DEVICE, IMAGING DEVICE, ELECTRONIC EQUIPMENT, A/D CONVERTER AND A/D CONVERSION METHOD 审中-公开
    固态成像装置，成像装置，电子设备，A / D转换器和A / D转换方法

    公开(公告)号：US20140211055A1

    公开(公告)日：2014-07-31

    申请号：US14244482

    申请日：2014-04-03

    Applicant: Sony Corporation

    Inventor： Hayato Wakabayashi ,  Masaru Kikuchi ,  Hiroshi Iwasa ,  Yuuki Yamagata

    IPC: H04N5/357 ,  H04N5/3745 ,  H03M1/08

    CPC classification number: H04N5/357 ,  H03M1/0658 ,  H03M1/08 ,  H03M1/1023 ,  H03M1/1205 ,  H03M1/123 ,  H03M1/129 ,  H03M1/34 ,  H03M1/56 ,  H03M1/745 ,  H04N5/335 ,  H04N5/37455 ,  H04N5/378

    Abstract: In a reference signal comparison AD conversion scheme, a reference signal SLP_ADC and each of P and D phases of a pixel signal voltage Vx are compared. A count clock CKcnt1 is counted based on the comparison result. The counting result data is converted into signal data Dsig, i.e., the difference between the P and D phases, which is also subjected to CDS. At this time, the n-bit AD conversion is performed on each of the P and D phases of the pixel signal voltage Vx, followed by summation for digital integration. This prevents any possible detrimental effects that may be caused by summation in the analog domain. Although the signal data becomes W times greater, noise will likely become √W times greater. This alleviates the problem of random noise resulting from AD conversion such as quantizing noise and circuit noise that do not exist in the analog domain, thus reducing the noise.

    Abstract translation: 在参考信号比较AD转换方案中，比较参考信号SLP_ADC和像素信号电压Vx的P和D相位中的每一个。 基于比较结果对计数时钟CKcnt1进行计数。 计数结果数据被转换为信号数据Dsig，也就是也经历CDS的P相和D相之间的差。 此时，对像素信号电压Vx的P相和D相进行n位AD转换，然后进行数字积分的求和。 这可以防止可能由模拟域中的相加引起的任何可能的有害影响。 虽然信号数据变为W倍，噪声可能会增加到更多的√W倍。 这减轻了AD转换产生的随机噪声的问题，例如量化噪声和模拟域中不存在的电路噪声，从而降低噪声。

    SOLID-STATE IMAGING APPARATUS WITH PLURAL READOUT MODES, AND ELECTRONIC EQUIPMENT
    5.
    发明申请
    SOLID-STATE IMAGING APPARATUS WITH PLURAL READOUT MODES, AND ELECTRONIC EQUIPMENT 审中-公开
    具有多种读出模式的固态成像装置和电子设备

    公开(公告)号：US20140014823A1

    公开(公告)日：2014-01-16

    申请号：US14032236

    申请日：2013-09-20

    Applicant: SONY CORPORATION

    Inventor： Yuichiro Araki ,  Masaru Kikuchi

    IPC: H04N5/378

    CPC classification number: H04N5/378 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H04N5/3456 ,  H04N5/3742 ,  H04N5/37455 ,  H04N9/045 ,  H04N9/04511

    Abstract: A solid-state imaging apparatus includes: a pixel array section in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix form, and a plurality of systematic pixel drive lines to transmit drive signals to read out signals from the pixels are arranged for each pixel row; and a row scanning section to simultaneously output the drive signals through the plurality of systematic pixel drive lines to a plurality of pixel rows for different pixel columns.

    Abstract translation: 一种固体摄像装置，具备：像素阵列部，其中包含光电转换元件的像素以矩阵形状二维排列;以及多个系统像素驱动线，用于发送驱动信号以从像素读出信号; 对于每个像素行; 以及行扫描部，其将通过所述多个系统像素驱动线的驱动信号同时输出到用于不同像素列的多个像素行。

    Solid-state imaging device, imaging device, electronic equipment, A/D converter and A/D conversion method
    6.
    发明授权
    Solid-state imaging device, imaging device, electronic equipment, A/D converter and A/D conversion method 有权
    固态成像装置，成像装置，电子设备，A / D转换器和A / D转换方法

    公开(公告)号：US08743254B2

    公开(公告)日：2014-06-03

    申请号：US13936563

    申请日：2013-07-08

    Applicant: Sony Corporation

    Inventor： Hayato Wakabayashi ,  Masaru Kikuchi ,  Hiroshi Iwasa ,  Yuuki Yamagata

    IPC: H04N5/335 ,  H01L27/00

    CPC classification number: H04N5/357 ,  H03M1/0658 ,  H03M1/08 ,  H03M1/1023 ,  H03M1/1205 ,  H03M1/123 ,  H03M1/129 ,  H03M1/34 ,  H03M1/56 ,  H03M1/745 ,  H04N5/335 ,  H04N5/37455 ,  H04N5/378

    Abstract: In a reference signal comparison AD conversion scheme, a reference signal SLP_ADC and each of P and D phases of a pixel signal voltage VX are compared. A count clock CKcnt1 is counted based on the comparison result. The counting result data is converted into signal data Dsig, i.e., the difference between the P and D phases, which is also subjected to CDS. At this time, the n-bit AD conversion is performed on each of the P and D phases of the pixel signal voltage VX, followed by summation for digital integration. This prevents any possible detrimental effects that may be caused by summation in the analog domain. Although the signal data becomes W times greater, noise will likely become √W times greater. This alleviates the problem of random noise resulting from AD conversion such as quantizing noise and circuit noise that do not exist in the analog domain, thus reducing the noise.

    Abstract translation: 在参考信号比较AD转换方案中，比较参考信号SLP_ADC和像素信号电压VX的P和D相位中的每一个。 基于比较结果对计数时钟CKcnt1进行计数。 计数结果数据被转换为信号数据Dsig，也就是也经历CDS的P相和D相之间的差。 此时，对像素信号电压VX的P相和D相进行n位AD转换，然后进行数字积分的求和。 这可以防止可能由模拟域中的相加引起的任何可能的有害影响。 虽然信号数据变为W倍，噪声可能会增加到更多的√W倍。 这减轻了AD转换产生的随机噪声的问题，例如量化噪声和模拟域中不存在的电路噪声，从而降低噪声。

    SOLID-STATE IMAGING DEVICE, IMAGING DEVICE, ELECTRONIC EQUIPMENT, A/D CONVERTER AND A/D CONVERSION METHOD
    7.
    发明申请
    SOLID-STATE IMAGING DEVICE, IMAGING DEVICE, ELECTRONIC EQUIPMENT, A/D CONVERTER AND A/D CONVERSION METHOD 有权
    固态成像装置，成像装置，电子设备，A / D转换器和A / D转换方法

    公开(公告)号：US20130293754A1

    公开(公告)日：2013-11-07

    申请号：US13936563

    申请日：2013-07-08

    Applicant: Sony Corporation

    Inventor： Hayato Wakabayashi ,  Masaru Kikuchi ,  Hiroshi Iwasa ,  Yuuki Yamagata

    IPC: H04N5/357 ,  H03M1/34 ,  H04N5/378

    CPC classification number: H04N5/357 ,  H03M1/0658 ,  H03M1/08 ,  H03M1/1023 ,  H03M1/1205 ,  H03M1/123 ,  H03M1/129 ,  H03M1/34 ,  H03M1/56 ,  H03M1/745 ,  H04N5/335 ,  H04N5/37455 ,  H04N5/378

    Abstract: In a reference signal comparison AD conversion scheme, a reference signal SLP_ADC and each of P and D phases of a pixel signal voltage VX are compared. A count clock CKcnt1 is counted based on the comparison result. The counting result data is converted into signal data Dsig, i.e., the difference between the P and D phases, which is also subjected to CDS. At this time, the n-bit AD conversion is performed on each of the P and D phases of the pixel signal voltage VX, followed by summation for digital integration. This prevents any possible detrimental effects that may be caused by summation in the analog domain. Although the signal data becomes W times greater, noise will likely become √W times greater. This alleviates the problem of random noise resulting from AD conversion such as quantizing noise and circuit noise that do not exist in the analog domain, thus reducing the noise.

    Abstract translation: 在参考信号比较AD转换方案中，比较参考信号SLP_ADC和像素信号电压VX的P和D相位中的每一个。 基于比较结果对计数时钟CKcnt1进行计数。 计数结果数据被转换为信号数据Dsig，也就是也经历CDS的P相和D相之间的差。 此时，对像素信号电压VX的P相和D相进行n位AD转换，然后进行数字积分的求和。 这可以防止可能由模拟域中的相加引起的任何可能的有害影响。 虽然信号数据变为W倍，噪声可能会增加到更多的√W倍。 这减轻了AD转换产生的随机噪声的问题，例如量化噪声和模拟域中不存在的电路噪声，从而降低噪声。

    Timing adjustment circuit, solid-state image pickup element, and camera system
    8.
    发明授权
    Timing adjustment circuit, solid-state image pickup element, and camera system 有权

    公开(公告)号：US08502578B2

    公开(公告)日：2013-08-06

    申请号：US13674555

    申请日：2012-11-12

    Applicant: Sony Corporation

    Inventor： Masahiro Hatano ,  Masaru Kikuchi

    IPC: H03L7/06

    CPC classification number: H01L27/14609 ,  H03L7/0805 ,  H03L7/0995 ,  H03L7/183 ,  H04L7/0012 ,  H04L7/0041 ,  H04N5/225

    Abstract: A timing adjustment circuit includes at least one data line; a phase synchronization circuit that includes a plurality of oscillation delay elements which oscillate an oscillation signal, and that is configured to oscillate the oscillation signal by synchronizing a phase of a feedback clock with a phase of a reference clock; at least one delay circuit that includes a delay element which is disposed on the data line and which is equivalent to one of the plurality of oscillation delay elements, and that is configured to delay data which is to be transmitted on the data line; and a delay adjustment unit configured to adjust an amount of delay of the delay element of the delay circuit in accordance with a signal associated with oscillation of the phase synchronization circuit.

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