公开(公告)号：US07461218B2

公开(公告)日：2008-12-02

申请号：US11171716

申请日：2005-06-29

申请人： Sridhar Muthrasanallur ,  Jeff Wilder ,  Chitra Natarajan

发明人： Sridhar Muthrasanallur ,  Jeff Wilder ,  Chitra Natarajan

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F13/1668

摘要： A memory read request is received at a port from a device, wherein the port is connected to the device by a packet-based link. The memory read request is enqueued into a small request queue or a large request queue based on an amount of data requested in the memory read request. Memory read requests are interleave dequeued between the small request queue and the large request queue based on an interleave granularity.

摘要翻译： 在来自设备的端口处接收到存储器读取请求，其中端口通过基于分组的链路连接到设备。 存储器读取请求基于存储器读请求中请求的数据量排入小请求队列或大请求队列。 存储器读取请求在小请求队列和基于交织粒度的大请求队列之间进行交织。

公开(公告)号：US20070005913A1

公开(公告)日：2007-01-04

申请号：US11171716

申请日：2005-06-29

申请人： Sridhar Muthrasanallur ,  Jeff Wilder ,  Chitra Natarajan

发明人： Sridhar Muthrasanallur ,  Jeff Wilder ,  Chitra Natarajan

IPC分类号： G06F13/00

CPC分类号： G06F13/1668

摘要： A memory read request is received at a port from a device, wherein the port is connected to the device by a packet-based link. The memory read request is enqueued into a small request queue or a large request queue based on an amount of data requested in the memory read request. Memory read requests are interleave dequeued between the small request queue and the large request queue based on an interleave granularity.

摘要翻译： 在来自设备的端口处接收到存储器读取请求，其中端口通过基于分组的链路连接到设备。 存储器读取请求基于存储器读请求中请求的数据量排入小请求队列或大请求队列。 存储器读取请求在小请求队列和基于交织粒度的大请求队列之间进行交织。

公开(公告)号：US09378173B2

公开(公告)日：2016-06-28

申请号：US12704470

申请日：2010-02-11

申请人： Mahesh U. Wagh ,  Wilfred W. Kwok ,  Sridhar Muthrasanallur

发明人： Mahesh U. Wagh ,  Wilfred W. Kwok ,  Sridhar Muthrasanallur

IPC分类号： G06F3/00 ,  G06F13/40 ,  H04L12/801 ,  H04L12/40

CPC分类号： G06F13/4059 ,  H04L12/4013 ,  H04L47/10

摘要： An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a “retry” event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the “available” amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset.

摘要翻译： 一种用于使用I / O控制器中包含的信用管理逻辑使I / O控制器中的缓冲器利用率最大化的装置和方法。 信用管理逻辑跟踪I / O控制器中可用的存储器信用数量，并与连接到I / O控制器的芯片组通信可用存储器信用量。 然后，芯片组可以向I / O控制器发送一定量的数据，该数量等于或小于通信的可用量的存储器信用以减少“重试”事件的发生。 通过比较I / O控制器中的每个缓冲器中的可用存储器并且指定I / O控制器的“可用”存储器量是相当于包含在I / O控制器中的存储器量的量 具有最少可用内存的缓冲区。 然后可以将这个“可用”量的I / O控制器存储器转换成存储器信用并传送到芯片组。

公开(公告)号：US20130132636A1

公开(公告)日：2013-05-23

申请号：US13690931

申请日：2012-11-30

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F13/42

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US20130091317A1

公开(公告)日：2013-04-11

申请号：US13691016

申请日：2012-11-30

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F13/40

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US20110208925A1

公开(公告)日：2011-08-25

申请号：US12861439

申请日：2010-08-23

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F13/14 ,  G06F12/00

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

摘要翻译： 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US07949794B2

公开(公告)日：2011-05-24

申请号：US11592341

申请日：2006-11-02

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Fallk ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Ellezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Fallk ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Ellezer Weissmann ,  Doron Shamia

IPC分类号： G06F3/00 ,  G06F13/14

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing /extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

摘要翻译： 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20100332686A1

公开(公告)日：2010-12-30

申请号：US12689899

申请日：2010-01-19

申请人： Kenneth C. Creta ,  Aaron T. Spink ,  Lance E. Hacking ,  Sridhar Muthrasanallur ,  Jasmin Ajanovic

发明人： Kenneth C. Creta ,  Aaron T. Spink ,  Lance E. Hacking ,  Sridhar Muthrasanallur ,  Jasmin Ajanovic

IPC分类号： G06F3/00 ,  G06F12/08 ,  G06F5/00

CPC分类号： G06F13/4027

摘要： Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.

摘要翻译： 处理写事务的系统和方法提供了根据I / O集线器和处理器之间的协议在输入/输出（I / O）集线器上组合写事务。 与写入事务相关的数据可以刷新到I / O设备，而不需要I / O设备内的专有软件和专用寄存器。

公开(公告)号：US07676603B2

公开(公告)日：2010-03-09

申请号：US10828872

申请日：2004-04-20

申请人： Kenneth C. Creta ,  Aaron T. Spink ,  Lance E. Hacking ,  Sridhar Muthrasanallur ,  Jasmin Ajanovic

发明人： Kenneth C. Creta ,  Aaron T. Spink ,  Lance E. Hacking ,  Sridhar Muthrasanallur ,  Jasmin Ajanovic

IPC分类号： G06F3/00

CPC分类号： G06F13/4027

摘要： Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.

摘要翻译： 处理写事务的系统和方法提供了根据I / O集线器和处理器之间的协议在输入/输出（I / O）集线器上组合写事务。 与写入事务相关的数据可以刷新到I / O设备，而不需要I / O设备内的专有软件和专用寄存器。

公开(公告)号：US20080162762A1

公开(公告)日：2008-07-03

申请号：US11618456

申请日：2006-12-29

申请人： Gilbert Neiger ,  Rajesh Sankaran Modukkarumukumana ,  Sridhar Muthrasanallur ,  Sebastian Schoenberg ,  Richard A. Uhlig

发明人： Gilbert Neiger ,  Rajesh Sankaran Modukkarumukumana ,  Sridhar Muthrasanallur ,  Sebastian Schoenberg ,  Richard A. Uhlig

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/45533 ,  G06F9/4812

摘要： Embodiments of apparatuses, methods, and systems for interrupt remapping based on requestor identification are disclosed. In one embodiment, an apparatus includes look-up logic, and comparison logic. The look-up logic is to look-up an entry associated with an interrupt request in a data structure. The comparison logic is to compare an identifier of the requestor to a source value in the entry.

摘要翻译： 公开了基于请求者识别的用于中断重映射的装置，方法和系统的实施例。 在一个实施例中，一种装置包括查找逻辑和比较逻辑。 查找逻辑是查找与数据结构中的中断请求相关联的条目。 比较逻辑是将请求者的标识符与条目中的源值进行比较。