Integrated process modulation (IPM) a novel solution for gapfill with HDP-CVD
    1.
    发明授权
    Integrated process modulation (IPM) a novel solution for gapfill with HDP-CVD 失效
    集成过程调制(IPM)是HDP-CVD填缝的新解决方案

    公开(公告)号:US07524750B2

    公开(公告)日:2009-04-28

    申请号:US11553772

    申请日:2006-10-27

    IPC分类号: H01L21/20

    CPC分类号: H01L21/76224

    摘要: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The silicon oxide film is deposited over the substrate with a halogen concentration less than 1.0%. The silicon oxide film is deposited with the plasma using a process that has simultaneous deposition and sputtering components. The flow rate of the halogen source to the process chamber to the flow rate of the silicon source to the process chamber is substantially between 0.5 and 3.0.

    摘要翻译: 提供了一种在设置在处理室中的衬底上沉积氧化硅膜的工艺。 包括卤素源,流动气体,硅源和氧化性气体反应物的处理气体流入处理室。 从处理气体形成具有至少1011个离子/ cm 3的离子密度的等离子体。 氧化硅膜以低于1.0%的卤素浓度沉积在衬底上。 使用具有同时沉积和溅射组分的工艺,用等离子体沉积氧化硅膜。 卤素源到处理室的流速与硅源到处理室的流速基本上在0.5和3.0之间。

    INTEGRATED PROCESS MODULATION (IPM) A NOVEL SOLUTION FOR GAPFILL WITH HDP-CVD
    2.
    发明申请
    INTEGRATED PROCESS MODULATION (IPM) A NOVEL SOLUTION FOR GAPFILL WITH HDP-CVD 失效
    集成过程调制(IPM)用于HDP-CVD的GAPFILL的新颖解决方案

    公开(公告)号:US20070243693A1

    公开(公告)日:2007-10-18

    申请号:US11553772

    申请日:2006-10-27

    IPC分类号: H01L21/76

    CPC分类号: H01L21/76224

    摘要: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The silicon oxide film is deposited over the substrate with a halogen concentration less than 1.0%. The silicon oxide film is deposited with the plasma using a process that has simultaneous deposition and sputtering components. The flow rate of the halogen source to the process chamber to the flow rate of the silicon source to the process chamber is substantially between 0.5 and 3.0.

    摘要翻译: 提供了一种在设置在处理室中的衬底上沉积氧化硅膜的工艺。 包括卤素源,流动气体,硅源和氧化性气体反应物的处理气体流入处理室。 从处理气体形成离子密度为至少10 11个/ cm 3的等离子体。 氧化硅膜以低于1.0%的卤素浓度沉积在衬底上。 使用具有同时沉积和溅射组分的工艺,用等离子体沉积氧化硅膜。 卤素源到处理室的流速与硅源到处理室的流速基本上在0.5和3.0之间。

    Low stress STI films and methods
    4.
    发明申请
    Low stress STI films and methods 有权
    低应力STI膜和方法

    公开(公告)号:US20070087515A1

    公开(公告)日:2007-04-19

    申请号:US11252400

    申请日:2005-10-17

    IPC分类号: H01L21/76

    摘要: The present invention generally relates to low compressive stress doped silicate glass films for STI applications. By way of non-limited example, the stress-lowering dopant may be a fluorine dopant, a germanium dopant, or a phosphorous dopant. The low compressive stress STI films will generally exhibit a compressive stress of less than 180 MPa, and preferably less than about 170 MPa. In certain embodiment, the STI films of the invention will exhibit a compressive stress less than about 100 MPa. Further, in certain embodiments, the low compressive stress STI films of the invention will comprise between about 0.1 and 25 atomic % of the stress-lowering dopant.

    摘要翻译: 本发明一般涉及用于STI应用的低压应力掺杂硅酸盐玻璃膜。 作为非限制性实例,应力降低掺杂剂可以是氟掺杂剂,锗掺杂剂或磷掺杂剂。 低压应力STI膜通常表现出小于180MPa,优选小于约170MPa的压缩应力。 在某些实施方案中,本发明的STI膜将表现出小于约100MPa的压缩应力。 此外,在某些实施方案中,本发明的低压应力STI膜将包含应力降低掺杂剂的约0.1至25原子%。