Integrated process modulation (IPM) a novel solution for gapfill with HDP-CVD
    1.
    发明授权
    Integrated process modulation (IPM) a novel solution for gapfill with HDP-CVD 失效
    集成过程调制(IPM)是HDP-CVD填缝的新解决方案

    公开(公告)号:US07524750B2

    公开(公告)日:2009-04-28

    申请号:US11553772

    申请日:2006-10-27

    IPC分类号: H01L21/20

    CPC分类号: H01L21/76224

    摘要: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The silicon oxide film is deposited over the substrate with a halogen concentration less than 1.0%. The silicon oxide film is deposited with the plasma using a process that has simultaneous deposition and sputtering components. The flow rate of the halogen source to the process chamber to the flow rate of the silicon source to the process chamber is substantially between 0.5 and 3.0.

    摘要翻译: 提供了一种在设置在处理室中的衬底上沉积氧化硅膜的工艺。 包括卤素源,流动气体,硅源和氧化性气体反应物的处理气体流入处理室。 从处理气体形成具有至少1011个离子/ cm 3的离子密度的等离子体。 氧化硅膜以低于1.0%的卤素浓度沉积在衬底上。 使用具有同时沉积和溅射组分的工艺,用等离子体沉积氧化硅膜。 卤素源到处理室的流速与硅源到处理室的流速基本上在0.5和3.0之间。

    INTEGRATED PROCESS MODULATION (IPM) A NOVEL SOLUTION FOR GAPFILL WITH HDP-CVD
    2.
    发明申请
    INTEGRATED PROCESS MODULATION (IPM) A NOVEL SOLUTION FOR GAPFILL WITH HDP-CVD 失效
    集成过程调制(IPM)用于HDP-CVD的GAPFILL的新颖解决方案

    公开(公告)号:US20070243693A1

    公开(公告)日:2007-10-18

    申请号:US11553772

    申请日:2006-10-27

    IPC分类号: H01L21/76

    CPC分类号: H01L21/76224

    摘要: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The silicon oxide film is deposited over the substrate with a halogen concentration less than 1.0%. The silicon oxide film is deposited with the plasma using a process that has simultaneous deposition and sputtering components. The flow rate of the halogen source to the process chamber to the flow rate of the silicon source to the process chamber is substantially between 0.5 and 3.0.

    摘要翻译: 提供了一种在设置在处理室中的衬底上沉积氧化硅膜的工艺。 包括卤素源,流动气体,硅源和氧化性气体反应物的处理气体流入处理室。 从处理气体形成离子密度为至少10 11个/ cm 3的等离子体。 氧化硅膜以低于1.0%的卤素浓度沉积在衬底上。 使用具有同时沉积和溅射组分的工艺,用等离子体沉积氧化硅膜。 卤素源到处理室的流速与硅源到处理室的流速基本上在0.5和3.0之间。

    IMPURITY CONTROL IN HDP-CVD DEP/ETCH/DEP PROCESSES
    4.
    发明申请
    IMPURITY CONTROL IN HDP-CVD DEP/ETCH/DEP PROCESSES 失效
    HDP-CVD DEP / ETCH / DEP工艺中的污染控制

    公开(公告)号:US20090068853A1

    公开(公告)日:2009-03-12

    申请号:US12204523

    申请日:2008-09-04

    IPC分类号: H01L21/314

    摘要: Methods are disclosed of depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A first portion of the silicon oxide film is deposited over the substrate and within the gap using a high-density plasma process. Thereafter, a portion of the deposited first portion of the silicon oxide film is etched back. This includes flowing a halogen precursor through a first conduit from a halogen-precursor source to the substrate processing chamber, forming a high-density plasma from the halogen precursor, and terminating flowing the halogen precursor after the portion has been etched back. Thereafter, a halogen scavenger is flowed to the substrate processing chamber to react with residual halogen in the substrate processing chamber. Thereafter, a second portion of the silicon oxide film is deposited over the first portion of the silicon oxide film and within the gap using a high-density plasma process.

    摘要翻译: 公开了在设置在基板处理室中的基板上沉积氧化硅膜的方法。 基板在相邻的凸起表面之间形成间隙。 氧化硅膜的第一部分使用高密度等离子体工艺沉积在衬底上并在间隙内。 此后,将氧化硅膜的沉积的第一部分的一部分回蚀刻。 这包括使卤素前体通过第一导管从卤素前体源流到基底处理室,从卤素前体形成高密度等离子体,并且在部分已被回蚀后终止流动卤素前体。 此后,卤素清除剂流到基板处理室以与基板处理室中的残留卤素反应。 此后,使用高密度等离子体处理,在氧化硅膜的第一部分和间隙内沉积第二部分氧化硅膜。

    Impurity control in HDP-CVD DEP/ETCH/DEP processes
    5.
    发明授权
    Impurity control in HDP-CVD DEP/ETCH/DEP processes 失效
    HDP-CVD DEP / ETCH / DEP工艺中的杂质控制

    公开(公告)号:US07745350B2

    公开(公告)日:2010-06-29

    申请号:US12204523

    申请日:2008-09-04

    IPC分类号: H01L21/311 H01L21/3065

    摘要: Methods are disclosed of depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A first portion of the silicon oxide film is deposited over the substrate and within the gap using a high-density plasma process. Thereafter, a portion of the deposited first portion of the silicon oxide film is etched back. This includes flowing a halogen precursor through a first conduit from a halogen-precursor source to the substrate processing chamber, forming a high-density plasma from the halogen precursor, and terminating flowing the halogen precursor after the portion has been etched back. Thereafter, a halogen scavenger is flowed to the substrate processing chamber to react with residual halogen in the substrate processing chamber. Thereafter, a second portion of the silicon oxide film is deposited over the first portion of the silicon oxide film and within the gap using a high-density plasma process.

    摘要翻译: 公开了在设置在基板处理室中的基板上沉积氧化硅膜的方法。 基板在相邻的凸起表面之间形成间隙。 氧化硅膜的第一部分使用高密度等离子体工艺沉积在衬底上并在间隙内。 此后,将氧化硅膜的沉积的第一部分的一部分回蚀刻。 这包括使卤素前体通过第一导管从卤素前体源流到基底处理室,从卤素前体形成高密度等离子体,并且在该部分被回蚀后终止流动卤素前体。 此后,卤素清除剂流到基板处理室以与基板处理室中的残留卤素反应。 此后,使用高密度等离子体处理,在氧化硅膜的第一部分和间隙内沉积第二部分氧化硅膜。

    REDUCTION OF ETCH-RATE DRIFT IN HDP PROCESSES
    6.
    发明申请
    REDUCTION OF ETCH-RATE DRIFT IN HDP PROCESSES 有权
    降低HDP工艺中的蚀刻速率

    公开(公告)号:US20090075489A1

    公开(公告)日:2009-03-19

    申请号:US12204503

    申请日:2008-09-04

    IPC分类号: H01L21/31

    摘要: A processing chamber is seasoned by providing a flow of season precursors to the processing chamber. A high-density plasma is formed from the season precursors by applying at least 7500 W of source power distributed with greater than 70% of the source power at a top of the processing chamber. A season layer having a thickness of at least 5000 Å is deposited at one point using the high-density plasma. Each of multiple substrates is transferred sequentially into the processing chamber to perform a process that includes etching. The processing chamber is cleaned between sequential transfers of the substrates.

    摘要翻译: 通过向处理室提供季节前体的流动来调节处理室。 通过在处理室的顶部施加分配有大于70%的源功率的至少7500W的源功率,从季节前体形成高密度等离子体。 使用高密度等离子体在一个点沉积具有至少5000埃的厚度的季节层。 将多个基板中的每一个依次传送到处理室中以执行包括蚀刻的处理。 在基板的顺序转印之间清洁处理室。

    GAPFILL EXTENSION OF HDP-CVD INTEGRATED PROCESS MODULATION SIO2 PROCESS
    7.
    发明申请
    GAPFILL EXTENSION OF HDP-CVD INTEGRATED PROCESS MODULATION SIO2 PROCESS 审中-公开
    GAPFILL扩展HDP-CVD集成过程调制SIO2过程

    公开(公告)号:US20080299775A1

    公开(公告)日:2008-12-04

    申请号:US11757637

    申请日:2007-06-04

    IPC分类号: H01L21/311

    摘要: Methods are disclosed for depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A silicon-containing gas, an oxygen-containing gas, and a fluent gas are flowed into the substrate processing chamber. A high-density plasma is formed from the silicon-containing gas, the oxygen-containing gas, and the fluent gas. A first portion of the silicon oxide film is deposited using the high-density plasma at a deposition rate between 900 and 6000 Å/min and with a deposition/sputter ratio greater than 30. The deposition/sputter ratio is defined as a ratio of a net deposition rate and a blanket sputtering rate to the blanket sputtering rate. Thereafter, a portion of the deposited first portion of the silicon oxide film is etched. A second portion of the silicon oxide film is deposited over the etched portion of the silicon oxide film.

    摘要翻译: 公开了用于在设置在基板处理室中的基板上沉积氧化硅膜的方法。 基板在相邻的凸起表面之间形成间隙。 含硅气体,含氧气体和流动气体流入衬底处理室。 由含硅气体,含氧气体和流动气体形成高密度等离子体。 使用高密度等离子体以900和6000 / min之间的沉积速率并且沉积/溅射比大于30沉积氧化硅膜的第一部分。沉积/溅射比定义为 净沉积速率和覆盖溅射速率的覆盖溅射速率。 此后,蚀刻氧化硅膜的沉积的第一部分的一部分。 氧化硅膜的第二部分沉积在氧化硅膜的蚀刻部分上。

    MULTI-STEP DEP-ETCH-DEP HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION PROCESSES FOR DIELECTRIC GAPFILLS
    8.
    发明申请
    MULTI-STEP DEP-ETCH-DEP HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION PROCESSES FOR DIELECTRIC GAPFILLS 审中-公开
    多级DEP-ETCH-DEP高密度等离子体化学气相沉积工艺用于电介质

    公开(公告)号:US20080142483A1

    公开(公告)日:2008-06-19

    申请号:US11947619

    申请日:2007-11-29

    IPC分类号: B44C1/22

    摘要: A method of forming a dielectric material in a substrate gap using a high-density plasma is described. The method may include depositing a first portion of the dielectric material into the gap with the high-density plasma. The deposition may form a protruding structure that at least partially blocks the deposition of the dielectric material into the gap. The first portion of dielectric material is exposed to an etchant that includes reactive species from a mixture that includes NH3 and NF3. The etchant forms a solid reaction product with the protruding structure, and the solid reaction product may be removed from the substrate. A final portion of the dielectric material may be deposited in the gap with the high-density plasma.

    摘要翻译: 描述了使用高密度等离子体在衬底间隙中形成电介质材料的方法。 该方法可以包括将电介质材料的第一部分沉积到具有高密度等离子体的间隙中。 沉积可以形成至少部分地阻挡介电材料沉积到间隙中的突出结构。 电介质材料的第一部分暴露于包括来自包括NH 3和N N 3 3的混合物的反应物质的蚀刻剂。 蚀刻剂形成具有突出结构的固体反应产物,并且固体反应产物可以从基底上除去。 介电材料的最终部分可以与高密度等离子体在间隙中沉积。