Integrated process modulation (IPM) a novel solution for gapfill with HDP-CVD
    1.
    发明授权
    Integrated process modulation (IPM) a novel solution for gapfill with HDP-CVD 失效
    集成过程调制(IPM)是HDP-CVD填缝的新解决方案

    公开(公告)号:US07524750B2

    公开(公告)日:2009-04-28

    申请号:US11553772

    申请日:2006-10-27

    IPC分类号: H01L21/20

    CPC分类号: H01L21/76224

    摘要: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The silicon oxide film is deposited over the substrate with a halogen concentration less than 1.0%. The silicon oxide film is deposited with the plasma using a process that has simultaneous deposition and sputtering components. The flow rate of the halogen source to the process chamber to the flow rate of the silicon source to the process chamber is substantially between 0.5 and 3.0.

    摘要翻译: 提供了一种在设置在处理室中的衬底上沉积氧化硅膜的工艺。 包括卤素源,流动气体,硅源和氧化性气体反应物的处理气体流入处理室。 从处理气体形成具有至少1011个离子/ cm 3的离子密度的等离子体。 氧化硅膜以低于1.0%的卤素浓度沉积在衬底上。 使用具有同时沉积和溅射组分的工艺,用等离子体沉积氧化硅膜。 卤素源到处理室的流速与硅源到处理室的流速基本上在0.5和3.0之间。

    INTEGRATED PROCESS MODULATION (IPM) A NOVEL SOLUTION FOR GAPFILL WITH HDP-CVD
    2.
    发明申请
    INTEGRATED PROCESS MODULATION (IPM) A NOVEL SOLUTION FOR GAPFILL WITH HDP-CVD 失效
    集成过程调制(IPM)用于HDP-CVD的GAPFILL的新颖解决方案

    公开(公告)号:US20070243693A1

    公开(公告)日:2007-10-18

    申请号:US11553772

    申请日:2006-10-27

    IPC分类号: H01L21/76

    CPC分类号: H01L21/76224

    摘要: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The silicon oxide film is deposited over the substrate with a halogen concentration less than 1.0%. The silicon oxide film is deposited with the plasma using a process that has simultaneous deposition and sputtering components. The flow rate of the halogen source to the process chamber to the flow rate of the silicon source to the process chamber is substantially between 0.5 and 3.0.

    摘要翻译: 提供了一种在设置在处理室中的衬底上沉积氧化硅膜的工艺。 包括卤素源,流动气体,硅源和氧化性气体反应物的处理气体流入处理室。 从处理气体形成离子密度为至少10 11个/ cm 3的等离子体。 氧化硅膜以低于1.0%的卤素浓度沉积在衬底上。 使用具有同时沉积和溅射组分的工艺,用等离子体沉积氧化硅膜。 卤素源到处理室的流速与硅源到处理室的流速基本上在0.5和3.0之间。

    MULTI-STEP DEP-ETCH-DEP HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION PROCESSES FOR DIELECTRIC GAPFILLS
    3.
    发明申请
    MULTI-STEP DEP-ETCH-DEP HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION PROCESSES FOR DIELECTRIC GAPFILLS 审中-公开
    多级DEP-ETCH-DEP高密度等离子体化学气相沉积工艺用于电介质

    公开(公告)号:US20080142483A1

    公开(公告)日:2008-06-19

    申请号:US11947619

    申请日:2007-11-29

    IPC分类号: B44C1/22

    摘要: A method of forming a dielectric material in a substrate gap using a high-density plasma is described. The method may include depositing a first portion of the dielectric material into the gap with the high-density plasma. The deposition may form a protruding structure that at least partially blocks the deposition of the dielectric material into the gap. The first portion of dielectric material is exposed to an etchant that includes reactive species from a mixture that includes NH3 and NF3. The etchant forms a solid reaction product with the protruding structure, and the solid reaction product may be removed from the substrate. A final portion of the dielectric material may be deposited in the gap with the high-density plasma.

    摘要翻译: 描述了使用高密度等离子体在衬底间隙中形成电介质材料的方法。 该方法可以包括将电介质材料的第一部分沉积到具有高密度等离子体的间隙中。 沉积可以形成至少部分地阻挡介电材料沉积到间隙中的突出结构。 电介质材料的第一部分暴露于包括来自包括NH 3和N N 3 3的混合物的反应物质的蚀刻剂。 蚀刻剂形成具有突出结构的固体反应产物,并且固体反应产物可以从基底上除去。 介电材料的最终部分可以与高密度等离子体在间隙中沉积。

    PROCESS SEQUENCE FOR FORMATION OF PATTERNED HARD MASK FILM (RFP) WITHOUT NEED FOR PHOTORESIST OR DRY ETCH
    5.
    发明申请
    PROCESS SEQUENCE FOR FORMATION OF PATTERNED HARD MASK FILM (RFP) WITHOUT NEED FOR PHOTORESIST OR DRY ETCH 有权
    用于形成图形硬片(RFP)的过程序列,不需要用于光刻胶或干蚀刻

    公开(公告)号:US20090208880A1

    公开(公告)日:2009-08-20

    申请号:US12034000

    申请日:2008-02-20

    IPC分类号: G03F7/00 C23F1/00

    摘要: Method and systems for patterning a hardmask film using ultraviolet light is disclosed according to one embodiment of the invention. Embodiments of the present invention alleviate the processing problem of depositing and etching photoresist in order to produce a hardmask pattern. A hardmask layer, such as, silicon oxide, is first deposited on a substrate within a deposition chamber. In some cases, the hardmask layer is baked or annealed following deposition. After which, portions of the hardmask layer are exposed with ultraviolet light. The ultraviolet light produces a pattern of exposed and unexposed portions of hardmask material. Following the exposure, an etching process, such as a wet etch, may occur that removes the unexposed portions of the hardmask. Following the etch, the hardmask may be annealed, baked or subjected to a plasma treatment.

    摘要翻译: 根据本发明的一个实施方案公开了使用紫外光图案化硬掩膜的方法和系统。 本发明的实施例减轻了沉积和蚀刻光刻胶的处理问题,以产生硬掩模图案。 首先将诸如氧化硅的硬掩模层沉积在沉积室内的衬底上。 在一些情况下,硬掩模层在沉积之后被烘烤或退火。 之后,硬掩模层的一部分用紫外线照射。 紫外光产生硬掩模材料的暴露和未曝光部分的图案。 曝光后,可能会发生腐蚀过程,例如湿蚀刻,从而去除硬掩模的未曝光部分。 在蚀刻之后,可以对硬掩模进行退火,烘烤或进行等离子体处理。

    Process sequence for formation of patterned hard mask film (RFP) without need for photoresist or dry etch
    6.
    发明授权
    Process sequence for formation of patterned hard mask film (RFP) without need for photoresist or dry etch 有权
    用于形成图案化硬掩模膜(RFP)的工艺顺序,无需光致抗蚀剂或干蚀刻

    公开(公告)号:US08153348B2

    公开(公告)日:2012-04-10

    申请号:US12034000

    申请日:2008-02-20

    IPC分类号: G03F7/26

    摘要: Method and systems for patterning a hardmask film using ultraviolet light is disclosed according to one embodiment of the invention. Embodiments of the present invention alleviate the processing problem of depositing and etching photoresist in order to produce a hardmask pattern. A hardmask layer, such as, silicon oxide, is first deposited on a substrate within a deposition chamber. In some cases, the hardmask layer is baked or annealed following deposition. After which, portions of the hardmask layer are exposed with ultraviolet light. The ultraviolet light produces a pattern of exposed and unexposed portions of hardmask material. Following the exposure, an etching process, such as a wet etch, may occur that removes the unexposed portions of the hardmask. Following the etch, the hardmask may be annealed, baked or subjected to a plasma treatment.

    摘要翻译: 根据本发明的一个实施方案公开了使用紫外光图案化硬掩膜的方法和系统。 本发明的实施例减轻了沉积和蚀刻光刻胶的处理问题,以产生硬掩模图案。 首先将诸如氧化硅的硬掩模层沉积在沉积室内的衬底上。 在一些情况下,硬掩模层在沉积之后被烘烤或退火。 之后,硬掩模层的一部分用紫外线照射。 紫外光产生硬掩模材料的暴露和未曝光部分的图案。 曝光后,可能会发生腐蚀过程,例如湿蚀刻,从而去除硬掩模的未曝光部分。 在蚀刻之后,可以对硬掩模进行退火,烘烤或进行等离子体处理。