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公开(公告)号：US20130290582A1
公开(公告)日：2013-10-31
申请号：US13455744
申请日：2012-04-25
申请人： Srinivasa Rao Kothamasu , Debjit Roy Choudhury , Dharmesh Kishor Tirthdasani , Sajith K. A. , Jean Jacob
发明人： Srinivasa Rao Kothamasu , Debjit Roy Choudhury , Dharmesh Kishor Tirthdasani , Sajith K. A. , Jean Jacob
IPC分类号： G06F13/00
CPC分类号： G06F13/404
摘要： A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus matrices, determining whether the master device has more than one default slave unit associated therewith, and, when the master device has more than one default slave unit associated therewith, generating first and second address mappings and configuring the system to have no more than one default slave unit per master device.
摘要翻译： 提供了一种用于映射一个或多个从设备之间的地址和多层互连系统中的至少一个对应的主设备的方法和设备，该多层互连系统包括用于在一个或多个从设备与主设备之间进行接口的多个总线矩阵。 所述方法和装置可操作用于接收对应于系统的地址映射，通过至少一个总线矩阵接收关于一个或多个从属设备的连通性的信息，确定主设备是否具有多于一个与之相关的默认从单元， 并且当所述主设备具有多于一个与之相关联的默认从单元时，产生第一和第二地址映射，并且将所述系统配置为每个主设备具有不超过一个默认从单元。
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公开(公告)号：US08667196B2
公开(公告)日：2014-03-04
申请号：US13455744
申请日：2012-04-25
申请人： Srinivasa Rao Kothamasu , Debjit Roy Choudhury , Dharmesh Kishor Tirthdasani , Sajith Kizhakke Kalathil Achuthan Kutty , Jean Jacob
发明人： Srinivasa Rao Kothamasu , Debjit Roy Choudhury , Dharmesh Kishor Tirthdasani , Sajith Kizhakke Kalathil Achuthan Kutty , Jean Jacob
IPC分类号： G06F13/00
CPC分类号： G06F13/404
摘要： A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus matrices, determining whether the master device has more than one default slave unit associated therewith, and, when the master device has more than one default slave unit associated therewith, generating first and second address mappings and configuring the system to have no more than one default slave unit per master device.
摘要翻译： 提供了一种用于映射一个或多个从设备之间的地址和多层互连系统中的至少一个对应的主设备的方法和设备，该多层互连系统包括用于在一个或多个从设备与主设备之间进行接口的多个总线矩阵。 所述方法和装置可操作用于接收对应于系统的地址映射，通过至少一个总线矩阵接收关于一个或多个从属设备的连通性的信息，确定主设备是否具有多于一个与之相关的默认从单元， 并且当所述主设备具有多于一个与之相关联的默认从单元时，产生第一和第二地址映射，并且将所述系统配置为每个主设备具有不超过一个默认从单元。
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3.发明授权Method and apparatus for decreasing leakage power consumption in power gated memories 有权降低功率门控存储器漏电功耗的方法和装置公开(公告)号：US08923087B2
公开(公告)日：2014-12-30
申请号：US13354222
申请日：2012-01-19
申请人： Romeshkumar Bharatkumar Mehta , Dharmesh Kishor Tirthdasani , Srinivasa Rao Kothamasu , Ravindra Bidnur
发明人： Romeshkumar Bharatkumar Mehta , Dharmesh Kishor Tirthdasani , Srinivasa Rao Kothamasu , Ravindra Bidnur
CPC分类号： G06F1/324 , G06F1/3275 , G11C5/148 , Y02D10/126 , Y02D10/13 , Y02D10/14
摘要： A method of controlling a power mode of a memory device is provided, which includes providing a power mode control signal responsive to a control signal and frequency information. The control signal is provided by a processing device operatively coupled to the memory device. The frequency information is associated with a clock signal used to operate the processing device, and the power mode control signal is operative to control the power mode. The control signal includes a chip select (CS) signal and/or a wait-for-interrupt (WFI) signal, and the power mode includes a light sleep (LS) mode and/or a deep sleep (DS) mode. The frequency information represents a low frequency range, medium frequency range, and/or high frequency range. A corresponding computer-readable medium, power management controller, and electronic system are also disclosed.
摘要翻译： 提供了一种控制存储器件的功率模式的方法，其包括响应于控制信号和频率信息提供功率模式控制信号。 控制信号由可操作地耦合到存储器件的处理设备提供。 频率信息与用于操作处理装置的时钟信号相关联，并且功率模式控制信号用于控制功率模式。 控制信号包括芯片选择（CS）信号和/或等待中断（WFI）信号，并且功率模式包括轻睡眠（LS）模式和/或深度睡眠（DS）模式。 频率信息表示低频范围，中频范围和/或高频范围。 还公开了相应的计算机可读介质，功率管理控制器和电子系统。
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4.发明申请公开(公告)号：US20130191665A1
公开(公告)日：2013-07-25
申请号：US13354222
申请日：2012-01-19
申请人： Romeshkumar Bharatkumar Mehta , Dharmesh Kishor Tirthdasani , Srinivasa Rao Kothamasu , Ravindra Bidnur
发明人： Romeshkumar Bharatkumar Mehta , Dharmesh Kishor Tirthdasani , Srinivasa Rao Kothamasu , Ravindra Bidnur
CPC分类号： G06F1/324 , G06F1/3275 , G11C5/148 , Y02D10/126 , Y02D10/13 , Y02D10/14
摘要： A method of controlling a power mode of a memory device is provided, which includes providing a power mode control signal responsive to a control signal and frequency information. The control signal is provided by a processing device operatively coupled to the memory device. The frequency information is associated with a clock signal used to operate the processing device, and the power mode control signal is operative to control the power mode. The control signal includes a chip select (CS) signal and/or a wait-for-interrupt (WFI) signal, and the power mode includes a light sleep (LS) mode and/or a deep sleep (DS) mode. The frequency information represents a low frequency range, medium frequency range, and/or high frequency range. A corresponding computer-readable medium, power management controller, and electronic system are also disclosed.
摘要翻译： 提供了一种控制存储器件的功率模式的方法，其包括响应于控制信号和频率信息提供功率模式控制信号。 控制信号由可操作地耦合到存储器件的处理设备提供。 频率信息与用于操作处理装置的时钟信号相关联，并且功率模式控制信号用于控制功率模式。 控制信号包括片选（CS）信号和/或等待中断（WFI）信号，并且功率模式包括轻睡眠（LS）模式和/或深睡眠（DS）模式。 频率信息表示低频范围，中频范围和/或高频范围。 还公开了相应的计算机可读介质，功率管理控制器和电子系统。
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5.发明授权Method and apparatus to reduce a quantity of error detection/correction bits in memory coupled to a data-protected processor port 有权用于减少与数据保护的处理器端口耦合的存储器中的错误检测/校正位的量的方法和装置公开(公告)号：US08707133B2
公开(公告)日：2014-04-22
申请号：US13311102
申请日：2011-12-05
CPC分类号： G06F11/10 , G06F11/1048 , G06F13/14 , H03M13/19 , H03M13/3776
摘要： An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.
摘要翻译： 用于接口处理设备和存储设备的接口设备包括纠错码（ECC）编码器，用于计算ECC比特，并且至少部分地基于由所述处理设备提供的数据，向处理设备提供ECC比特 存储器件，从而不需要将ECC位存储在存储器件中。 接口设备可以包括奇偶校验编码器，以根据由处理设备提供的数据提供奇偶校验位到存储器设备;以及奇偶解码器，用于根据数据有选择地修改ECC位， 奇偶校验位由存储器件提供。 ECC编码器可以提供ECC位，并且奇偶校验解码器可以基于由存储器件提供的数据和由存储器件提供的奇偶校验位来选择性地修改提供给处理器件的ECC位。
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6.发明申请Method and Apparatus to Reduce a Quantity of Error Detection/Correction Bits in Memory Coupled to a Data-Protected Processor Port 有权用于减少存储器中的错误检测/校正位数量的数据保护处理器端口的方法和装置公开(公告)号：US20130145227A1
公开(公告)日：2013-06-06
申请号：US13311102
申请日：2011-12-05
CPC分类号： G06F11/10 , G06F11/1048 , G06F13/14 , H03M13/19 , H03M13/3776
摘要： An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.
摘要翻译： 用于接口处理设备和存储设备的接口设备包括纠错码（ECC）编码器，用于计算ECC比特，并且至少部分地基于由所述处理设备提供的数据，向处理设备提供ECC比特 存储器件，从而不需要将ECC位存储在存储器件中。 接口设备可以包括奇偶校验编码器，以根据由处理设备提供的数据提供奇偶校验位到存储器设备;以及奇偶解码器，用于根据数据有选择地修改ECC位， 奇偶校验位由存储器件提供。 ECC编码器可以提供ECC位，并且奇偶校验解码器可以基于由存储器件提供的数据和由存储器件提供的奇偶校验位来选择性地修改提供给处理器件的ECC位。
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