Power governor for dynamic RAM
    6.
    发明授权
    Power governor for dynamic RAM 有权
    动态RAM功率调节器

    公开(公告)号:US06667929B1

    公开(公告)日:2003-12-23

    申请号:US10171863

    申请日:2002-06-14

    IPC分类号: G11C700

    摘要: Apparatus for limiting the power consumption of a random access memory (RAM), having in combination a counter for counting the number of memory commands in a sample interval, and power governor control logic responsive to the number of memory commands, for limiting the maximum number of transfer requests processed in a sample interval when the counter accumulates a count exceeding a predetermined value.

    摘要翻译: 用于限制随机存取存储器(RAM)的功耗的装置,其组合有用于对采样间隔中的存储器命令的数量进行计数的计数器和响应于存储器命令数量的功率调节器控制逻辑,用于限制最大数量 当计数器累积超过预定值的计数时,在采样间隔中处理的传送请求。

    Computer RAM memory system with enhanced scrubbing and sparing
    7.
    发明授权
    Computer RAM memory system with enhanced scrubbing and sparing 失效
    具有增强擦洗和备用功能的电脑RAM存储系统

    公开(公告)号:US06480982B1

    公开(公告)日:2002-11-12

    申请号:US09325814

    申请日:1999-06-04

    IPC分类号: G11C2900

    CPC分类号: G11C29/70 G06F11/106

    摘要: In a computer RAM memory system, the memory is subjected to a self test operation during which data is written to and read out from each address location of the memory. The data read out is compared with the written data to detect errors and the number of errors at each bit position is counted. When the number of errors in a bit position-exceeds a selected threshold, the corresponding DRAM is replaced by a spare DRAM. When the self test detects two or more errors in the same double word, the DRAM corresponding to the bit position having the highest error count is replaced with a spare DRAM. The memory is periodically scrubbed and errors detected during the scrubbing operation are counted for each bit position. At the end of the scrubbing of a chip row the DRAMs corresponding to bit positions at which the error counts exceed a selected threshold are replaced with spare DRAMs. When a multiple bit error in a double word is detected during scrubbing, the corresponding double word is tagged.

    摘要翻译: 在计算机RAM存储器系统中,存储器经受自检操作,在此期间数据被写入存储器的每个地址位置并从其读出。 将读出的数据与写入的数据进行比较以检测错误,并对每个位位置处的错误数进行计数。 当比特位置的错误数量超过所选择的阈值时,相应的DRAM被备用DRAM替代。 当自检检测到同一双字中的两个或多个错误时,与具有最高错误计数的位位置相对应的DRAM被替换为备用DRAM。 周期性擦洗存储器,并在每个位位置对擦洗操作期间检测到的错误进行计数。 在擦除芯片行结束时,对应于错误计数超过所选阈值的位位置的DRAM被替换为备用DRAM。 当在擦除期间检测到双字中的多位错误时,对应的双字被标记。

    Multi-cycle symbol level error correction and memory system

    公开(公告)号:US07028248B2

    公开(公告)日:2006-04-11

    申请号:US09796285

    申请日:2001-02-28

    IPC分类号: H03H13/00

    摘要: Symbol level multi-cycle error correction and detection coding systems are developed and deployed in computer memory architectures resulting in an increase in robustness in terms of single bus line failures having no effect on the robustness of the coding technique and capabilities. The multi-cycle symbol level error correction techniques of the present invention also provide a mechanism for reducing the pin-out requirements for memory chips and dual in-line memory modules. The resulting ECC circuitry is thus simpler and consumes less real estate.

    Barcode scanner with adjustable light source intensity
    10.
    发明授权
    Barcode scanner with adjustable light source intensity 失效
    条码扫描器,光源强度可调

    公开(公告)号:US5581071A

    公开(公告)日:1996-12-03

    申请号:US350579

    申请日:1994-12-06

    IPC分类号: G06K7/10

    CPC分类号: G06K7/10851 G06K2207/1018

    摘要: A barcode scanner, which is particularly suitable for reading barcode information from surfaces having various reflective properties, includes a light intensity control for the light source of the barcode scanner. The light intensity control preferably comprises a means for ramping voltage and a summing circuit which allows the current flowing through the light source to be controlled. In addition, the light intensity control utilizes a clocking means which controls the rate of voltage ramping.

    摘要翻译: 特别适用于从具有各种反射特性的表面读取条形码信息的条形码扫描仪包括条形码扫描器的光源的光强度控制。 光强度控制优选地包括用于斜坡电压的装置和允许流过光源的电流被控制的求和电路。 此外,光强度控制利用控制电压斜坡率的计时装置。