公开(公告)号：US20050221557A1

公开(公告)日：2005-10-06

申请号：US10812412

申请日：2004-03-30

申请人： Steve Wang ,  Kae-Horng Wang

发明人： Steve Wang ,  Kae-Horng Wang

IPC分类号： H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L29/66181 ,  H01L27/1087 ,  H01L29/945

摘要： The present invention provides a method for producing a deep trench capacitor in a semiconductor substrate (1) comprising the steps of: providing a first trench (2) in the semiconductor substrate (1); oxidizing the semiconductor substrate (1) in the first trench (2) for providing an oxidized silicon layer (3); depositing a conformal aluminium-oxide layer (4) in the first trench (2); removing the horizontal regions (5) of the deposited aluminium-oxide layer (4) and the oxidized silicon layer (3); providing a second trench (6) underneath the first trench (2); increasing the width of the second trench (6) to a widened second trench (7) for providing a bottle structure (8); depositing a dielectric layer (10) in the widened second trench (7) and filling the widened second trench (7) with a conductive filling (11).

摘要翻译： 本发明提供一种在半导体衬底（1）中制造深沟槽电容器的方法，包括以下步骤：在半导体衬底（1）中提供第一沟槽（2）; 氧化用于提供氧化硅层（3）的第一沟槽（2）中的半导体衬底（1）; 在第一沟槽（2）中沉积共形氧化铝层（4）; 去除沉积的氧化铝层（4）和氧化硅层（3）的水平区域（5）; 在所述第一沟槽（2）下方提供第二沟槽（6）; 将第二沟槽（6）的宽度增加到加宽的第二沟槽（7）以提供瓶结构（8）; 在所述加宽的第二沟槽（7）中沉积介电层（10）并用导电填料（11）填充所述加宽的第二沟槽（7）。

公开(公告)号：US07008849B2

公开(公告)日：2006-03-07

申请号：US10724903

申请日：2003-12-01

申请人： Grit Schwalbe ,  Kae-Horng Wang ,  Klaus Feldner ,  Elard Stein Von Kamienski

发明人： Grit Schwalbe ,  Kae-Horng Wang ,  Klaus Feldner ,  Elard Stein Von Kamienski

IPC分类号： H01L21/8236

CPC分类号： H01L27/11568 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/112

摘要： A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an isolating layer, a plurality of wordlines disposed in a second direction perpendicular to the first direction above the bitlines, and memory cells disposed at the points at which the bitlines and wordlines cross each other. According to a first aspect of the present invention, the isolating layer is removed from the bitlines at the portions that are not covered by the wordlines, whereas the areas between the bitlines remain unaffected. Alternatively, the isolating layer is removed from the whole cell array. Then, an electrical conductive material is provided on the exposed portions of the bitlines. The method is used to provide bitline contacts in a nitride read only memory (NROM™) chip.

摘要翻译： 一种用于在存储单元阵列中提供位线触点的方法包括沿第一方向布置的多个位线，位线由绝缘层覆盖，多个字线沿垂直于位线上方的第一方向的第二方向布置，以及 位于位线和字线彼此交叉的点处的存储单元。 根据本发明的第一方面，在未被字线覆盖的部分处，从位线移除隔离层，而位线之间的区域保持不受影响。 或者，从整个电池阵列中去除绝缘层。 然后，在位线的露出部分上设置导电材料。 该方法用于在氮化物只读存储器（NROM TM））芯片中提供位线触点。

公开(公告)号：US06984578B2

公开(公告)日：2006-01-10

申请号：US10476355

申请日：2002-04-11

申请人： Wolfgang Gustin ,  Kae-Horng Wang ,  Matthias Kroenke

发明人： Wolfgang Gustin ,  Kae-Horng Wang ,  Matthias Kroenke

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76816 ,  H01L27/115 ,  H01L27/11521

摘要： The invention relates to a method for the production of an integrated circuit, comprising the following steps: a substrate (1) is provided with at least one first, second and third gate stack (GS1, GS2, GS3) of approximately the same height surface of said substrate, a common active area (60) being provided on the surface of the substrate in said substrate (1) between the first and second gate stack (GS1, GS2); a first insulating layer (70) is provided in order to cover the embedding of the first second and third gate stack (GS1, GS2, GS3); the upper side of a gate connection (20) of the third gate stack (GS3) is uncovered; a second insulating layer (80) is provided in order to cover the upper side of a gate connection (20); a mask (M2) is provided on the resulting structure having a first opening (12a) above the uncovered upper side of the gate connection (20) of the third gate stack (GS3), a second opening (F2b) above the substrate (1) between the third and second gate stack (GS3, GS2) and a third opening (F2c) above the common active area (60), partially overlapping the first and second gate stack (GS1, GS2), and simultaneously forming a first, second and third contact hole (KB, KS, KG) using said mask (32) in an etching process, the first contact hole (KB) uncovering the common active area (60) on the surface of the substrate between the first and second gate stack (GS1, GS2), the second contact hole (KS) uncovering the surface of the substrate between the second and third gate stack (GS2, GS2) and the third contact hole (KG) uncovering the upper side of the gate connection (20) of the third gate stack (GS3).

摘要翻译： 本发明涉及一种用于生产集成电路的方法，包括以下步骤：衬底（1）设置有至少一个第一，第二和第三栅堆叠（GS 1，GS 2，GS 3） 所述衬底的相同高度表面，在第一和第二栅极堆叠（GS 1，GS 2）之间的所述衬底（1）的衬底的表面上设置公共有源区（60）; 提供第一绝缘层（70）以覆盖第一第二和第三栅极堆叠（GS 1，GS 2，GS 3）的嵌入; 第三栅极堆叠（GS 3）的栅极连接（20）的上侧未被覆盖; 设置第二绝缘层（80）以覆盖栅极连接（20）的上侧; 在所得到的结构上设置掩模（M 2），其具有在第三栅极堆叠（GS 3）的栅极连接（20）的未覆盖的上侧上方的第一开口（12a），第二开口（F2b） 在第三和第二栅极堆叠（GS 3，GS 2）之间的衬底（1）上方和公共有效区域（60）上方的第三开口（F 2 c）之上，部分地与第一和第二栅极堆叠（GS1， GS 2），并且在蚀刻工艺中使用所述掩模（32）同时形成第一，第二和第三接触孔（KB，KS，KG），所述第一接触孔（KB）露出所述公共有效区域 在第一和第二栅极堆叠（GS1，GS2）之间的衬底表面，第二接触孔（KS）露出第二和第三栅极堆叠（GS 2，GS 2）和第三接触之间的衬底表面 孔（KG）露出第三栅极堆叠（GS3）的栅极连接（20）的上侧。

公开(公告)号：US07265405B2

公开(公告)日：2007-09-04

申请号：US10754439

申请日：2004-01-09

申请人： Kae-Horng Wang ,  Ralf Staub ,  Matthias Krönke

发明人： Kae-Horng Wang ,  Ralf Staub ,  Matthias Krönke

IPC分类号： H01L29/94

CPC分类号： H01L27/10888 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10829

摘要： One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged on the active areas with which contact is to be made. The control lines may, for example, be gate lines. The semiconductor component is fabricated in the following way: application of a polysilicon layer to the semiconductor wafer, patterning of the polysilicon layer, in order to produce a polysilicon contact above the active area, the polysilicon contact at least partly covering the two control lines, application of a first insulator layer to the semiconductor wafer, with the polysilicon contact being embedded, partial removal of the first insulator layer, so that at least the upper surface of the polysilicon contact is uncovered, and application of a metal layer to the semiconductor wafer in order to make electrical contact with the polysilicon contact.

摘要翻译： 在半导体晶片的一个或多个有源区上产生一个（或多个）触点，一个或多个隔离的控制线可以布置在与其进行接触的有源区上。 控制线可以例如是栅极线。 以下列方式制造半导体部件：向半导体晶片施加多晶硅层，构图多晶硅层，以在有源区上方产生多晶硅接触，多晶硅接触至少部分覆盖两个控制线， 将第一绝缘体层施加到半导体晶片，其中嵌入多晶硅接触部分地去除第一绝缘体层，使得至少多晶硅接触的上表面未被覆盖，以及向半导体晶片施加金属层 以便与多晶硅接触进行电接触。