公开(公告)号：US07008849B2

公开(公告)日：2006-03-07

申请号：US10724903

申请日：2003-12-01

申请人： Grit Schwalbe ,  Kae-Horng Wang ,  Klaus Feldner ,  Elard Stein Von Kamienski

发明人： Grit Schwalbe ,  Kae-Horng Wang ,  Klaus Feldner ,  Elard Stein Von Kamienski

IPC分类号： H01L21/8236

CPC分类号： H01L27/11568 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/112

摘要： A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an isolating layer, a plurality of wordlines disposed in a second direction perpendicular to the first direction above the bitlines, and memory cells disposed at the points at which the bitlines and wordlines cross each other. According to a first aspect of the present invention, the isolating layer is removed from the bitlines at the portions that are not covered by the wordlines, whereas the areas between the bitlines remain unaffected. Alternatively, the isolating layer is removed from the whole cell array. Then, an electrical conductive material is provided on the exposed portions of the bitlines. The method is used to provide bitline contacts in a nitride read only memory (NROM™) chip.

摘要翻译： 一种用于在存储单元阵列中提供位线触点的方法包括沿第一方向布置的多个位线，位线由绝缘层覆盖，多个字线沿垂直于位线上方的第一方向的第二方向布置，以及 位于位线和字线彼此交叉的点处的存储单元。 根据本发明的第一方面，在未被字线覆盖的部分处，从位线移除隔离层，而位线之间的区域保持不受影响。 或者，从整个电池阵列中去除绝缘层。 然后，在位线的露出部分上设置导电材料。 该方法用于在氮化物只读存储器（NROM TM））芯片中提供位线触点。

公开(公告)号：US07660175B2

公开(公告)日：2010-02-09

申请号：US12040719

申请日：2008-02-29

申请人： Dieter Kohlert ,  Erhard Sixt ,  Rainer Holmer ,  Georg Seidemann ,  Berthold Schuderer ,  Gunther Mackh ,  Sabine Penka ,  Grit Schwalbe-Dietrich ,  Bernhard Duschinger ,  Josef Hermann

发明人： Dieter Kohlert ,  Erhard Sixt ,  Rainer Holmer ,  Georg Seidemann ,  Berthold Schuderer ,  Gunther Mackh ,  Sabine Penka ,  Grit Schwalbe-Dietrich ,  Bernhard Duschinger ,  Josef Hermann

IPC分类号： G11C7/00

CPC分类号： G11C29/48 ,  G11C29/1201 ,  G11C2029/0403

摘要： An embodiment of an integrated circuit comprises a plurality of cells. Each cell comprises a first supply node, a second supply node, a series connection with a first transistor, a second transistor and an electrical element. The series connection is coupled between the first and the second supply node. The electrical element includes a first and a second node. A third transistor is coupled between the first node of the electrical element and a first output node of the cell and a fourth transistor is coupled between the second node of the electrical element and the second output node of the cell. A control terminal of the first, the third and the fourth transistor is coupled to a first control node of the cell and a control terminal of the second transistor is coupled to a second control node of the cell.

摘要翻译： 集成电路的实施例包括多个单元。 每个单元包括第一电源节点，第二电源节点，与第一晶体管的串联连接，第二晶体管和电气元件。 串联连接耦合在第一和第二供电节点之间。 电气元件包括第一和第二节点。 第三晶体管耦合在电元件的第一节点和单元的第一输出节点之间，第四晶体管耦合在电元件的第二节点和单元的第二输出节点之间。 第一，第三和第四晶体管的控制端子耦合到单元的第一控制节点，并且第二晶体管的控制端耦合到单元的第二控制节点。

公开(公告)号：US20090219773A1

公开(公告)日：2009-09-03

申请号：US12040719

申请日：2008-02-29

申请人： Dieter Kohlert ,  Erhard Sixt ,  Rainer Holmer ,  Georg Seidemann ,  Berthold Schuderer ,  Gunther Mackh ,  Sabine Penka ,  Grit Schwalbe-Dietrich ,  Bernhard Duschinger ,  Josef Hermann

发明人： Dieter Kohlert ,  Erhard Sixt ,  Rainer Holmer ,  Georg Seidemann ,  Berthold Schuderer ,  Gunther Mackh ,  Sabine Penka ,  Grit Schwalbe-Dietrich ,  Bernhard Duschinger ,  Josef Hermann

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C29/48 ,  G11C29/1201 ,  G11C2029/0403

摘要： An embodiment of an integrated circuit comprises a plurality of cells. Each cell comprises a first supply node, a second supply node, a series connection with a first transistor, a second transistor and an electrical element. The series connection is coupled between the first and the second supply node. The electrical element includes a first and a second node. A third transistor is coupled between the first node of the electrical element and a first output node of the cell and a fourth transistor is coupled between the second node of the electrical element and the second output node of the cell. A control terminal of the first, the third and the fourth transistor is coupled to a first control node of the cell and a control terminal of the second transistor is coupled to a second control node of the cell.

摘要翻译： 集成电路的实施例包括多个单元。 每个单元包括第一电源节点，第二电源节点，与第一晶体管的串联连接，第二晶体管和电气元件。 串联连接耦合在第一和第二供电节点之间。 电气元件包括第一和第二节点。 第三晶体管耦合在电元件的第一节点和单元的第一输出节点之间，第四晶体管耦合在电元件的第二节点和单元的第二输出节点之间。 第一，第三和第四晶体管的控制端子耦合到单元的第一控制节点，并且第二晶体管的控制端耦合到单元的第二控制节点。

公开(公告)号：US20080070403A1

公开(公告)日：2008-03-20

申请号：US11985686

申请日：2007-11-16

申请人： Klaus Goller ,  Alexander Reb ,  Grit Schwalbe

发明人： Klaus Goller ,  Alexander Reb ,  Grit Schwalbe

IPC分类号： H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/76802 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In a method of contacting terminals, a substrate having a first terminal and a second terminal is provided, a terminal surface of the first terminal being located at a shorter distance from a substrate surface than a surface of the second terminal. A first insulating layer, in which a contact via is formed for exposing the terminal surface of the first terminal, is formed on the substrate surface. The contact via is filled with a conductive material, and a second insulating layer is formed on the first insulating layer and on the contact via filled with the conductive material. Using an etching mask, a first recess for exposing the conductive material filling the contact via, and a second recess are etched through the second and first insulating layers for exposing the second terminal surface. A conductive material for producing first and second contact terminals is introduced into the first and second recesses. This is to achieve that the second terminal is contacted in the production of the second contact terminal.

摘要翻译： 在接触端子的方法中，提供了具有第一端子和第二端子的基板，第一端子的端子表面位于比第二端子的表面离基板表面更短的距离处。 在基板表面上形成有第一绝缘层，其中形成用于暴露第一端子的端子表面的接触通孔。 接触通孔填充有导电材料，并且在第一绝缘层上形成第二绝缘层，并在接触孔上填充有导电材料。 使用蚀刻掩模，通过第二和第一绝缘层蚀刻用于暴露填充接触通孔的导电材料的第一凹部和第二凹槽，用于暴露第二端子表面。 用于产生第一和第二接触端子的导电材料被引入到第一和第二凹槽中。 这是为了实现在第二接触端子的制造中第二端子接触。

公开(公告)号：US07199060B2

公开(公告)日：2007-04-03

申请号：US10724141

申请日：2003-12-01

申请人： Grit Schwalbe ,  Thomas Ruder

发明人： Grit Schwalbe ,  Thomas Ruder

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/311

CPC分类号： H01L21/02063 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76802

摘要： The invention relates to a process for patterning dielectric layers. A photoresist layer is applied to the dielectric layer and patterned. Then, the pattern which has been predetermined by the resist mask is transferred to the dielectric layer. The incineration of the resist mask is carried out a temperature of 50° C. to 200° C., with the oxygen plasma being generated from a gas which has an oxygen content of 40 to 60% by volume. During a subsequent step of cleaning the patterned dielectric layer using dilute hydrofluoric acid, the trenches which have been introduced into the dielectric layer are widened to a significantly lesser extent than after incineration under the conditions which have previously been customary.

摘要翻译： 本发明涉及一种用于图案化电介质层的方法。 将光致抗蚀剂层施加到电介质层并图案化。 然后，通过抗蚀剂掩模预定的图案被转印到电介质层。 抗蚀剂掩模的焚化在50℃至200℃的温度下进行，氧等离子体由氧含量为40至60体积％的气体产生。 在使用稀氢氟酸清洗图案化电介质层的后续步骤中，已经引入电介质层的沟槽在先前已经习惯的条件下比在焚烧之后扩大到显着更小的程度。

公开(公告)号：US07666783B2

公开(公告)日：2010-02-23

申请号：US11985686

申请日：2007-11-16

申请人： Klaus Goller ,  Alexander Reb ,  Grit Schwalbe

发明人： Klaus Goller ,  Alexander Reb ,  Grit Schwalbe

IPC分类号： H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/76802 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In a method of contacting terminals, a substrate having a first terminal and a second terminal is provided, a terminal surface of the first terminal being located at a shorter distance from a substrate surface than a surface of the second terminal. A first insulating layer, in which a contact via is formed for exposing the terminal surface of the first terminal, is formed on the substrate surface. The contact via is filled with a conductive material, and a second insulating layer is formed on the first insulating layer and on the contact via filled with the conductive material. Using an etching mask, a first recess for exposing the conductive material filling the contact via, and a second recess are etched through the second and first insulating layers for exposing the second terminal surface. A conductive material for producing first and second contact terminals is introduced into the first and second recesses. This is to achieve that the second terminal is contacted in the production of the second contact terminal.

摘要翻译： 在接触端子的方法中，提供了具有第一端子和第二端子的基板，第一端子的端子表面位于比第二端子的表面离基板表面更短的距离处。 在基板表面上形成有第一绝缘层，其中形成用于暴露第一端子的端子表面的接触通孔。 接触通孔填充有导电材料，并且在第一绝缘层上形成第二绝缘层，并在接触孔上填充有导电材料。 使用蚀刻掩模，通过第二和第一绝缘层蚀刻用于暴露填充接触通孔的导电材料的第一凹部和第二凹槽，用于暴露第二端子表面。 用于产生第一和第二接触端子的导电材料被引入到第一和第二凹槽中。 这是为了实现在第二接触端子的制造中第二端子接触。