公开(公告)号：US20110062501A1

公开(公告)日：2011-03-17

申请号：US12561708

申请日：2009-09-17

申请人： Steven R. Soss ,  Andreas Knorr

发明人： Steven R. Soss ,  Andreas Knorr

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/4966 ,  H01L21/28114 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  Y10S438/926

摘要： Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the removable gate electrode and the substrate, removing a portion of the self aligned contact stop layer over the removable gate electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, e.g., a hafnium oxide, an aluminum oxide, or a silicon carbide and transforming the upper portion of the metal into a dielectric layer by oxidation, fluorination, or nitridation. Embodiments also include forming a hardmask layer over the removable gate electrode to protect the electrode during silicidation in source/drain regions of the semiconductor device.

摘要翻译： 具有替换栅电极和集成自对准触点的半导体器件由栅极电介质层和栅极线与触点之间的电隔离特性提高而形成。 实施例包括在衬底上形成可移除的栅电极，在可移除的栅电极和衬底之上形成自对准的接触止动层，在可移除的栅极电极和电极本身上移除一部分自对准接触停止层，留下开口， 在开口中形成金属的替代栅电极，将金属的上部转化成电介质层，并形成自对准的接触。 实施例包括形成电介质材料例如氧化铪，氧化铝或碳化硅的接触停止层，并通过氧化，氟化或氮化将金属的上部转化成电介质层。 实施例还包括在可移除的栅极电极上形成硬掩模层，以在半导体器件的源极/漏极区域中的硅化期间保护电极。

公开(公告)号：US08709882B2

公开(公告)日：2014-04-29

申请号：US12683759

申请日：2010-01-07

申请人： Steven R. Soss ,  Andreas Knorr

发明人： Steven R. Soss ,  Andreas Knorr

IPC分类号： H01L21/00

CPC分类号： H01L28/20

摘要： A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.

摘要翻译： 形成具有可控电阻的精密电阻器，以补偿随温度发生的变化。 一个实施例包括形成在衬底上具有宽度和长度的电阻半导体元件，跨越电阻半导体元件的宽度图形化导电线，但与之电隔离，并且在电气半导体元件下方形成耗尽沟道 导线来控制电阻半导体元件的电阻值。 该设计能够动态调节电阻，从而提高电阻器的可靠性或允许最终封装期间的电阻修改。

公开(公告)号：US20120068234A1

公开(公告)日：2012-03-22

申请号：US13239874

申请日：2011-09-22

申请人： Steven R. Soss ,  Andreas Knorr

发明人： Steven R. Soss ,  Andreas Knorr

IPC分类号： H01L29/772

CPC分类号： H01L29/4966 ,  H01L21/28114 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  Y10S438/926

摘要： Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the electrode and the substrate, removing a portion of the self aligned contact stop layer over the electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, and transforming the upper portion of the metal into a dielectric layer. Embodiments also include forming a hardmask layer over the removable gate electrode to protect the electrode during silicidation in source/drain regions of the semiconductor device.

摘要翻译： 具有替换栅电极和集成自对准触点的半导体器件由栅极电介质层和栅极线与触点之间的电隔离特性提高而形成。 实施例包括在衬底上形成可移除的栅电极，在电极和衬底之上形成自对准的接触停止层，在电极和电极本身上去除一部分自对准的接触阻挡层，留下开口，形成置换栅极 金属的电极，在开口中，将金属的上部转变为电介质层，并形成自对准的接触。 实施例包括形成电介质材料的接触停止层，并将金属的上部转化成电介质层。 实施例还包括在可移除的栅极电极上形成硬掩模层，以在半导体器件的源极/漏极区域中的硅化期间保护电极。

公开(公告)号：US08048790B2

公开(公告)日：2011-11-01

申请号：US12561708

申请日：2009-09-17

申请人： Steven R. Soss ,  Andreas Knorr

发明人： Steven R. Soss ,  Andreas Knorr

IPC分类号： H01L21/00

CPC分类号： H01L29/4966 ,  H01L21/28114 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  Y10S438/926

摘要： Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the removable gate electrode and the substrate, removing a portion of the self aligned contact stop layer over the removable gate electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, e.g., a hafnium oxide, an aluminum oxide, or a silicon carbide and transforming the upper portion of the metal into a dielectric layer by oxidation, fluorination, or nitridation. Embodiments also include forming a hardmask layer over the removable gate electrode to protect the electrode during silicidation in source/drain regions of the semiconductor device.

摘要翻译： 具有替换栅电极和集成自对准触点的半导体器件由栅极电介质层和栅极线与触点之间的电隔离特性提高而形成。 实施例包括在衬底上形成可移除的栅电极，在可移除的栅电极和衬底之上形成自对准的接触止动层，在可移除的栅极电极和电极本身上移除一部分自对准接触停止层，留下开口， 在开口中形成金属的替代栅电极，将金属的上部转化成电介质层，并形成自对准的接触。 实施例包括形成电介质材料例如氧化铪，氧化铝或碳化硅的接触停止层，并通过氧化，氟化或氮化将金属的上部转化成电介质层。 实施例还包括在可移除的栅极电极上形成硬掩模层，以在半导体器件的源极/漏极区域中的硅化期间保护电极。

公开(公告)号：US20110163417A1

公开(公告)日：2011-07-07

申请号：US12683759

申请日：2010-01-07

申请人： Steven R. Soss ,  Andreas Knorr

发明人： Steven R. Soss ,  Andreas Knorr

IPC分类号： H01L29/8605 ,  H01L21/02

CPC分类号： H01L28/20

摘要： A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.

摘要翻译： 形成具有可控电阻的精密电阻器，以补偿随温度发生的变化。 一个实施例包括形成在衬底上具有宽度和长度的电阻半导体元件，跨越电阻半导体元件的宽度图形化导电线，但与之电隔离，并且在电气半导体元件下方形成耗尽沟道 导线来控制电阻半导体元件的电阻值。 该设计能够动态调节电阻，从而提高电阻器的可靠性或允许最终封装期间的电阻修改。

公开(公告)号：US08940634B2

公开(公告)日：2015-01-27

申请号：US13171657

申请日：2011-06-29

申请人： Brett H. Engel ,  Lindsey Hall ,  David F. Hilscher ,  Randolph F. Knarr ,  Steven R. Soss ,  Jin Z. Wallner

发明人： Brett H. Engel ,  Lindsey Hall ,  David F. Hilscher ,  Randolph F. Knarr ,  Steven R. Soss ,  Jin Z. Wallner

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.

摘要翻译： 在半导体器件中形成重叠触点的方法包括在电介质层中形成第一触点; 蚀刻电介质层以形成与第一接触相邻的凹部，并且在蚀刻介电层的同时去除第一接触的顶部，其中在电介质层中形成凹部之后第一接触的底部保留在电介质层中 ; 以及在与所述第一接触件的底部相邻的所述凹部中形成第二触点，并且在所述第一接触件的底部的顶表面的顶部上形成第二接触。

公开(公告)号：US20130001786A1

公开(公告)日：2013-01-03

申请号：US13171657

申请日：2011-06-29

申请人： Brett H. Engel ,  Lindsey Hall ,  David F. Hilscher ,  Randolph F. Knarr ,  Steven R. Soss ,  Jin Z. Wallner

发明人： Brett H. Engel ,  Lindsey Hall ,  David F. Hilscher ,  Randolph F. Knarr ,  Steven R. Soss ,  Jin Z. Wallner

IPC分类号： H01L21/28 ,  H01L23/48

CPC分类号： H01L23/528 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.

摘要翻译： 在半导体器件中形成重叠触点的方法包括在电介质层中形成第一触点; 蚀刻电介质层以形成与第一接触相邻的凹部，并且在蚀刻介电层的同时去除第一接触的顶部，其中在电介质层中形成凹部之后第一接触的底部保留在电介质层中 ; 以及在与所述第一接触件的底部相邻的所述凹部中形成第二触点，并且在所述第一接触件的底部的顶表面的顶部上形成第二接触。

公开(公告)号：US20120038026A1

公开(公告)日：2012-02-16

申请号：US13282224

申请日：2011-10-26

申请人： Steven R. Soss

发明人： Steven R. Soss

IPC分类号： H01L27/06

CPC分类号： H01L27/0802 ,  H01L28/20 ,  H01L29/8605

摘要： A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate.

摘要翻译： 精密的低电容电阻器例如在体衬底中形成。 一个实施例包括在衬底上形成源极/漏极区域，图案化源/漏区域的一部分以形成段，蚀刻段以将每个段的上部部分与每个段的下部分基本上分离，并填充空间 在具有绝缘材料的段之间。 所得到的结构保持端部焊盘处的段之间的电连接，但是将电阻器段与底部衬底分开，从而避免与衬底的电容耦合。

公开(公告)号：US20110163389A1

公开(公告)日：2011-07-07

申请号：US12683770

申请日：2010-01-07

申请人： Steven R. Soss

发明人： Steven R. Soss

IPC分类号： H01L27/08 ,  H01L21/02

CPC分类号： H01L27/0802 ,  H01L28/20 ,  H01L29/8605

摘要： A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate.

摘要翻译： 精密的低电容电阻器例如在体衬底中形成。 一个实施例包括在衬底上形成源极/漏极区域，图案化源/漏区域的一部分以形成段，蚀刻段以将每个段的上部部分与每个段的下部分基本上分离，并填充空间 在具有绝缘材料的段之间。 所得到的结构保持端部焊盘处的段之间的电连接，但是将电阻器段与底部衬底分开，从而避免与衬底的电容耦合。

公开(公告)号：US09625557B2

公开(公告)日：2017-04-18

申请号：US14285059

申请日：2014-05-22

申请人： M. Brandon Steele ,  Steven R. Soss

发明人： M. Brandon Steele ,  Steven R. Soss

IPC分类号： G01R35/00 ,  G01R31/265

CPC分类号： G01R35/005 ,  G01R31/265

摘要： A method and a system for calibrating the work function or surface potential of a non-contact voltage sensor probe tip. The method includes preparing one or more reference sample surfaces and a reference non-contact voltage sensor probe tip to have stable surface potentials, measuring the voltage between the reference samples and the reference sensor probe tip, measuring the voltage between a point on a non-reference sample surface and the reference sensor probe tip, measuring the voltage between the same point on the non-reference sample surface and a non-reference non-contact voltage sensor probe tip, and determining a surface potential correction factor for the non-reference, non-contact voltage sensor.