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公开(公告)号：US20060156155A1
公开(公告)日：2006-07-13
申请号：US11027391
申请日：2004-12-29
CPC分类号： G06F11/0793 , G06F11/0724 , G06F12/0817 , G06F2212/1032 , Y10S707/99933 , Y10S707/99934
摘要： In one embodiment, the present invention includes a system, which may be a multiprocessor system having multiple nodes, each with a processor and a cache. The system may include a directory stored in a memory that includes entries having coherency information. At least one of the nodes may be configured to detect an error in an entry of the directory based on a coherency protocol. In some embodiments, the node may correct the error using state information obtained from other nodes. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种系统，其可以是具有多个节点的多处理器系统，每个具有处理器和高速缓存。 系统可以包括存储在包括具有一致性信息的条目的存储器中的目录。 可以将至少一个节点配置为基于一致性协议来检测目录的条目中的错误。 在一些实施例中，节点可以使用从其他节点获得的状态信息来校正错误。 描述和要求保护其他实施例。
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2.发明申请Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system 失效在锁定的双模块冗余系统中减少不可纠正的错误率公开(公告)号：US20070022348A1
公开(公告)日：2007-01-25
申请号：US11173835
申请日：2005-06-30
申请人： Paul Racunas , Joel Emer , Arijit Biswas , Shubhendu Mukherjee , Steven Raasch
发明人： Paul Racunas , Joel Emer , Arijit Biswas , Shubhendu Mukherjee , Steven Raasch
CPC分类号： G06F11/165 , G06F11/1641 , G06F11/1658 , G06F11/1683
摘要： Embodiments of apparatuses and methods for reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system are disclosed. In one embodiment, an apparatus includes two processor cores, a micro-checker, a global checker, and fault logic. The micro-checker is to detect whether a value from a structure in one core matches a value from the corresponding structure in the other core. The global checker is to detect lockstep failures between the two cores. The fault logic is to cause the two cores to be resynchronized if there is a lockstep error but the micro-checker has detected a mismatch.
摘要翻译： 公开了用于降低锁定双模块冗余系统中的不可校正错误率的装置和方法的实施例。 在一个实施例中，装置包括两个处理器核，微检查器，全局检验器和故障逻辑。 微检查器是检测来自一个核心中的结构的值是否与另一个核心中的相应结构的值匹配。 全局检查器是检测两个内核之间的锁步失败。 如果存在锁步错误但微检查器检测到不匹配，则故障逻辑是使两个内核重新同步。
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公开(公告)号：US20060095821A1
公开(公告)日：2006-05-04
申请号：US10953887
申请日：2004-09-29
IPC分类号： G06F9/44
CPC分类号： G06F11/1494 , G06F11/1695
摘要： A method and apparatus for a checker instruction in a redundant multithreading environment is described. In one embodiment, when RMT requires, a processor may issue a checker instruction in both a leading thread and a trailing thread. The checker instruction may travel down individual pipelines for each thread independently until it reaches a buffer at the end of each pipeline. Then, prior to committing the checker instruction, the checker instruction looks for its counterpart and does a comparison of the instructions. If the checker instructions match, the checker instructions commit and retires otherwise an error is declared.
摘要翻译： 描述用于冗余多线程环境中的检查指令的方法和装置。 在一个实施例中，当RMT需要时，处理器可以在前导线程和后退线程中发出校验指令。 检查器指令可以独立地沿着每个线程的各个管道下行，直到它到达每个管道末端的缓冲区。 然后，在提交检查指令之前，检验员指令寻找其对应方，并对指令进行比较。 如果检查器指令匹配，则检查器指令提交并退出，否则声明错误。
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4.发明申请Reducing false error detection in a microprocessor by tracking instructions neutral to errors 有权通过跟踪中性到错误的指令，减少微处理器中的错误检测公开(公告)号：US20050283685A1
公开(公告)日：2005-12-22
申请号：US10871429
申请日：2004-06-17
CPC分类号： G06F11/0721 , G06F9/30145 , G06F9/30181 , G06F9/3865 , G06F11/0751 , G06F11/1052 , G06F11/1407
摘要： A technique to reduce false error detection in microprocessors by tracking instructions neutral to errors. As an instruction is decoded, an anti-pi bit is tagged to the decoded instruction. When a parity error is detected, an instruction queue first checks if the anti-pi bit is set. If the anti-pi bit is set, then instruction is neutral to errors, and the pi bit need not be set. Prefetch, branch predict hint and NOP are types of instructions that are neutral to errors.
摘要翻译： 通过跟踪中性到错误的指令来减少微处理器中的错误检测的技术。 当指令被解码时，反码比特被标记到解码指令。 当检测到奇偶校验错误时，指令队列首先检查反pi位是否被设置。 如果反pi位被置位，则指令对于错误是中性的，并且不需要设置pi位。 预取，分支预测提示和NOP是对错误中立的指令类型。
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公开(公告)号：US20050050304A1
公开(公告)日：2005-03-03
申请号：US10651376
申请日：2003-08-29
申请人： Shubhendu Mukherjee , Steven Reinhardt , Joel Emer
发明人： Shubhendu Mukherjee , Steven Reinhardt , Joel Emer
CPC分类号： G06F11/366 , G06F9/3851 , G06F9/3863 , G06F11/1494 , G06F11/1629
摘要： Methods and apparatuses for incremental, periodic storage of checkpoints in a multi-threaded processor.
摘要翻译： 用于在多线程处理器中增量，定期存储检查点的方法和装置。
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6.发明申请Buffering unchecked stores for fault detection in redundant multithreading systems using speculative memory support 审中-公开使用推测内存支持，在冗余多线程系统中缓冲未检查的存储，以进行故障检测公开(公告)号：US20050193283A1
公开(公告)日：2005-09-01
申请号：US10749618
申请日：2003-12-30
CPC分类号： G06F11/1497
摘要： A multithreaded architecture is disclosed for buffering unchecked stores for fault detection in redundant multithreading systems using speculative memory support. In particular, the performance of a SRT processor is enhanced by using speculative memory support to buffer the leading threads stores until they can be compared with their trailing thread counterparts. Buffering these stores in the memory system allows them to be removed from the store buffer. Since the speculative memory system will have greater capacity than the store buffer, additional stores may be buffered before the leading thread will be forced to stall. This will result in an increase in slack between threads, and thus an increase in performance.
摘要翻译： 公开了一种多线程架构，用于使用推测性内存支持在冗余多线程系统中缓存未检查的存储以进行故障检测。 特别地，SRT处理器的性能通过使用推测性内存支持来缓冲领先的线程存储来增强，直到它们可以与其尾随线程对应来进行比较。 将这些存储缓冲在存储器系统中，可以将它们从存储缓冲区中删除。 由于推测性内存系统的容量会比存储缓冲区大，所以可能会在引导线程被迫停止之前缓存附加存储。 这将导致线程之间的松弛增加，从而导致性能的提高。
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7.发明申请Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support 有权使用推测内存支持，在冗余多线程系统中管理外部内存更新以进行故障检测公开(公告)号：US20050154944A1
公开(公告)日：2005-07-14
申请号：US10750039
申请日：2003-12-30
CPC分类号： G06F9/3851 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F11/1494 , G06F11/1497
摘要： A multithreaded architecture is disclosed for managing external memory updates for fault detection in redundant multithreading systems using speculative memory support. In particular, a method provides input replication of load values on a SRT processor by using speculative memory support to isolate redundant threads form external updates. This method thus avoids the need for dedicated structures to provide input replication.
摘要翻译： 公开了一种多线程体系结构，用于管理使用推测性内存支持的冗余多线程系统中的故障检测的外部存储器更新。 特别地，一种方法通过使用推测性存储器支持将冗余线程从外部更新隔离，从而在SRT处理器上提供负载值的输入复制。 因此，该方法避免了专用结构提供输入复制的需要。
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8.发明申请Method and apparatus for reducing false error detection in a redundant multi-threaded system 有权用于减少冗余多线程系统中的错误检测的方法和装置公开(公告)号：US20050283712A1
公开(公告)日：2005-12-22
申请号：US10948813
申请日：2004-09-22
CPC分类号： G06F9/3865 , G06F11/10
摘要： A technique to reduce false error detection in microprocessors within a redundant multi-threaded computing environment. A pi bit is propagated with at least two instructions through an instruction flow path. Results of executing the instruction are compared to see if an error has occurred and if so, the pi bits are examined to determine which instruction contains the error.
摘要翻译： 一种在冗余多线程计算环境中减少微处理器中的错误检测的技术。 通过指令流程路径，使用至少两个指令来传播pi位。 比较执行指令的结果，看是否发生错误，如果是，则检查pi位，以确定哪个指令包含错误。
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9.发明申请公开(公告)号：US20050283716A1
公开(公告)日：2005-12-22
申请号：US10871430
申请日：2004-06-17
CPC分类号： G06F9/3865 , G06F11/10
摘要： A technique to reduce false error detection in microprocessors. A pi bit is propagated with an instruction through an instruction flow path. When a parity error is detected, the pi bit is set, instead of raising a machine check exception. Upon reaching a commit point, the processor can determine if the instruction was on a wrong path.
摘要翻译： 减少微处理器中的错误检测的技术。 通过指令流程路径，通过指令传播pi位。 当检测到奇偶校验错误时，设置pi位，而不是提高机器检查异常。 达到提交点后，处理器可以确定指令是否在错误的路径上。
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10.发明申请Reducing false error detection in a microprocessor by tracking dynamically dead instructions 审中-公开通过跟踪动态死指令，减少微处理器中的错误检测公开(公告)号：US20050283590A1
公开(公告)日：2005-12-22
申请号：US10872109
申请日：2004-06-17
CPC分类号： G06F9/3865
摘要： A technique to reduce false error detection in microprocessors by tracking dynamically dead instructions. When an instruction commits, it is then stored in a PET buffer. A processor may now declare a machine check error when the instruction is being removed from the PET buffer rather than at the commit point. The processor can scan the PET buffer to determine if the instruction is a dynamically dead instruction. This further enables the processor to reduce false positives.
摘要翻译： 通过跟踪动态死指令来减少微处理器中的错误检测的技术。 当指令提交时，然后将其存储在PET缓冲器中。 当从PET缓冲区而不是在提交点移除指令时，处理器现在可以声明机器检查错误。 处理器可以扫描PET缓冲区，以确定指令是否是动态死指令。 这进一步使得处理器能够减少误报。
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