公开(公告)号：US5996594A

公开(公告)日：1999-12-07

申请号：US666189

申请日：1996-03-19

申请人： Sudipto Ranendra Roy ,  Iqbal Ali ,  Gregory B. Shinn ,  Rajani C. Shah ,  Shelley H. Peterman ,  Srini Raghavan

发明人： Sudipto Ranendra Roy ,  Iqbal Ali ,  Gregory B. Shinn ,  Rajani C. Shah ,  Shelley H. Peterman ,  Srini Raghavan

IPC分类号： B08B1/04 ,  B08B3/12 ,  B24B37/34 ,  B24D13/14 ,  H01L21/00 ,  H01L21/306 ,  B08B1/02 ,  C03C15/00 ,  C23G1/02

CPC分类号： H01L21/67028 ,  B08B1/04 ,  B08B3/12 ,  B24B37/345 ,  B24D13/145 ,  H01L21/02074 ,  Y10S134/902

摘要： A post chemical-mechanical polishing clean-up process. Particles and ionic and metallic contaminants remaining on wafer 32 surface after CMP are removed and scratches are smoothed. The wafer 32 may be subjected to a high pressure/high rotational speed rinse at spindle rinse station 42 followed by buffing of the wafer 32 on a second polishing platen 38. If desired, a second high pressure/high speed rinse at spindle rinse station 42 may be performed after the buffing step. The wafer 32 may then be then transferred to a tank 50 for a megasonic bath and after the megasonic bath, the wafer 32 is transferred to a scrubber 44, which scrubs both surfaces of the wafer 32 with brushes and then spins the wafer 32 dry as spin station 84. All transfers are performed in a solution such as DI water to prevent drying of slurry on the wafer surface.

摘要翻译： 后化学机械抛光清理过程。 在CMP之后残留在晶片32表面上的颗粒和离子和金属污染物被除去并且刮擦变得平滑。 晶片32可以在主轴漂洗站42处进行高压/高转速冲洗，随后在第二研磨台板38上抛光晶片32.如果需要，在主轴漂洗站42处进行第二次高压/高速冲洗 可以在抛光步骤之后进行。 然后可以将晶片32转移到用于兆声波槽的箱50中，并且在超声波浴之后，将晶片32转移到洗涤器44，擦洗器44用刷子擦洗晶片32的两个表面，然后将晶片32旋转干燥，如 旋转站84.所有转移在诸如去离子水的溶液中进行以防止在晶片表面上的浆料干燥。

公开(公告)号：US06436746B1

公开(公告)日：2002-08-20

申请号：US09225405

申请日：1999-01-05

申请人： Amitava Chatterjee ,  Wei William Lee ,  Greg A. Hames ,  Qizhi He ,  Maureen Hanratty ,  Iqbal Ali

发明人： Amitava Chatterjee ,  Wei William Lee ,  Greg A. Hames ,  Qizhi He ,  Maureen Hanratty ,  Iqbal Ali

IPC分类号： H01L21338

CPC分类号： H01L29/66545 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/76895 ,  H01L29/42376

摘要： A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer (22) may be formed adjacent a substrate (12). A disposable gate (24) may be formed adjacent the primary insulation layer (22). An isolation dielectric layer (26) may be formed adjacent the primary insulation layer (22). The disposable gate (24) may be removed to expose a portion of the primary insulation layer (22). The exposed portion of the primary insulation layer (22) may be removed to expose a portion of the substrate (12). The primary insulation layer (22) may be selectively removable relative to the isolation dielectric layer (26). A gate insulator (30) may be formed on the exposed portion of the substrate (12). A gate (32) may be formed adjacent the gate insulator (30).

摘要翻译： 制造可用于晶体管的改进的栅极结构的方法。 可以在基底（12）附近形成主绝缘层（22）。 可以在一次绝缘层（22）附近形成一次性门（24）。 隔离电介质层（26）可以邻近初级绝缘层（22）形成。 一次性门（24）可以被去除以暴露一次绝缘层（22）的一部分。 可以去除主绝缘层（22）的暴露部分以暴露衬底（12）的一部分。 主绝缘层（22）可以相对于隔离介电层（26）选择性地去除。 栅极绝缘体（30）可以形成在衬底（12）的暴露部分上。 栅极（32）可以形成在栅极绝缘体（30）附近。

公开(公告)号：US06307230B1

公开(公告)日：2001-10-23

申请号：US09416380

申请日：1999-10-12

申请人： Amitava Chatterjee ,  Wei William Lee ,  Greg A. Hames ,  Quzhi He ,  Iqbal Ali ,  Maureen A. Hanratty

发明人： Amitava Chatterjee ,  Wei William Lee ,  Greg A. Hames ,  Quzhi He ,  Iqbal Ali ,  Maureen A. Hanratty

IPC分类号： H01L2976

CPC分类号： H01L29/66628 ,  H01L21/31111 ,  H01L29/66545

摘要： A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

摘要翻译： 提供一种具有改进的侧壁栅极结构和结构方法的晶体管。 改进的侧壁栅极结构可以包括具有沟道区域（20）的半导体衬底（12）。 栅极绝缘体（36）可以邻近半导体衬底（12）的沟道区域（20）。 栅极（38）可以邻近栅极绝缘体（36）形成。 侧壁绝缘体（28）可以邻近门（38）的一部分形成。 侧壁绝缘体（28）由氮氧化硅材料构成。 外延层（30）可以邻近侧壁绝缘体（28）的一部分并且基本上在沟道区域（20）的外侧邻近半导体衬底（12）形成。 缓冲层（32）可以与侧壁绝缘体（28）的一部分相邻并且与外延层（30）相邻。

公开(公告)号：US06753559B2

公开(公告)日：2004-06-22

申请号：US09899199

申请日：2001-07-06

申请人： Amitava Chatterjee ,  Wei William Lee ,  Greg A. Hames ,  Qizhi He ,  Maureen Hanratty ,  Iqbal Ali

发明人： Amitava Chatterjee ,  Wei William Lee ,  Greg A. Hames ,  Qizhi He ,  Maureen Hanratty ,  Iqbal Ali

IPC分类号： H01L2980

CPC分类号： H01L29/66545 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/76895 ,  H01L29/42376

摘要： A gate structure which includes a semiconductor substrate having a channel region, a gate insulator adjacent the channel region of the semiconductor substrate and a conductible gate adjacent the gate insulator. A primary insulation layer is adjacent the semiconductor substrate, the primary insulation layer having an opening where the gate insulator contacts the semiconductor substrate and an isolation dielectric layer adjacent the primary insulation layer, the isolation dielectric layer having an opening where the conductible gate is located and the isolation dielectric layer having a silicon oxynitride material.

摘要翻译： 一种栅极结构，其包括具有沟道区的半导体衬底，与半导体衬底的沟道区相邻的栅极绝缘体和与栅极绝缘体相邻的导电栅极。 主绝缘层与半导体衬底相邻，第一绝缘层具有栅极绝缘体接触半导体衬底的开口和与初级绝缘层相邻的隔离电介质层，隔离电介质层具有可导电栅极所在的开口， 隔离电介质层具有氮氧化硅材料。

公开(公告)号：US5909628A

公开(公告)日：1999-06-01

申请号：US804484

申请日：1997-02-21

申请人： Amitava Chatterjee ,  Theodore W. Houston ,  Ih-Chin Chen ,  Agerico L. Esquirel ,  Somnath Nag ,  Iqbal Ali ,  Keith A. Joyner ,  Yin Hu ,  Jeffrey Alan McKee ,  Peter Stewart McAnally

发明人： Amitava Chatterjee ,  Theodore W. Houston ,  Ih-Chin Chen ,  Agerico L. Esquirel ,  Somnath Nag ,  Iqbal Ali ,  Keith A. Joyner ,  Yin Hu ,  Jeffrey Alan McKee ,  Peter Stewart McAnally

IPC分类号： H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/78

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  Y10S148/05

摘要： A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.

摘要翻译： 制造半导体器件或集成电路的技术产生平坦化的补充层，其在抛光之后具有比较均匀的厚度，例如通过化学机械抛光（CMP）。 在通常由场氧化物占据的衬底的该部分中的有源区域之间插入虚拟有源区，以便在这些区域中减少在CMP期间发生的“凹陷”。 虚拟有源区域可以采取大块，部分或完全形成的环形结构的形状，或者可以调节其面积密度以匹配衬底的该区域中的有源区的面积密度的多个柱。 支柱的设计规则可以是在多晶硅线或第一级金属化线被放置以避免寄生电容的地方放置柱子。

公开(公告)号：US6117741A

公开(公告)日：2000-09-12

申请号：US226237

申请日：1999-01-05

申请人： Amitava Chatterjee ,  Wei William Lee ,  Greg A. Hames ,  Quzhi He ,  Iqbal Ali ,  Maureen A. Hanratty

发明人： Amitava Chatterjee ,  Wei William Lee ,  Greg A. Hames ,  Quzhi He ,  Iqbal Ali ,  Maureen A. Hanratty

IPC分类号： H01L21/311 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L21/31111 ,  H01L29/66545

摘要： A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

摘要翻译： 提供一种具有改进的侧壁栅极结构和结构方法的晶体管。 改进的侧壁栅极结构可以包括具有沟道区域（20）的半导体衬底（12）。 栅极绝缘体（36）可以邻近半导体衬底（12）的沟道区域（20）。 栅极（38）可以邻近栅极绝缘体（36）形成。 侧壁绝缘体（28）可以邻近门（38）的一部分形成。 侧壁绝缘体（28）由氮氧化硅材料构成。 外延层（30）可以邻近侧壁绝缘体（28）的一部分并且基本上在沟道区域（20）的外侧邻近半导体衬底（12）形成。 缓冲层（32）可以邻近侧壁绝缘体（28）的一部分并且邻近外延层（30）形成。