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11 条记录 (耗时 0.035 秒)

    Semiconductor on silicon (SOI) transistor with a halo implant
    2.
    发明授权
    Semiconductor on silicon (SOI) transistor with a halo implant 失效
    具有卤素植入物的硅（SOI）晶体管的半导体

    公开(公告)号：US5936278A

    公开(公告)日：1999-08-10

    申请号：US813524

    申请日：1997-03-07

    申请人： Yin Hu ,  Jarvis B. Jacobs ,  Theodore W. Houston

    发明人： Yin Hu ,  Jarvis B. Jacobs ,  Theodore W. Houston

    IPC分类号： H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L21/336 ,  H01L21/822 ,  H01L27/12 ,  H01L29/10 ,  H01L29/732 ,  H01L29/786 ,  H01L27/01 ,  H01L31/0392

    CPC分类号： H01L29/1045 ,  H01L29/66265 ,  H01L29/66772 ,  H01L29/7317 ,  H01L29/78654

    摘要： A semiconductor over insulator transistor (100) includes a semiconductor mesa (36) formed over an insulating layer (34) which overlies a semiconductor substrate (32). Source and drain regions (66, 68) of a first conductivity type are formed at opposite ends of the mesa. A body node (56) of a second conductivity type is located between the source and drain regions in the mesa. A gate insulator (40) and a gate electrode (46) lie over the body node. Halo implants (54, 56) are placed to completely separate the source and drain regions from the body node, or channel regions, for improving short channel effect. The transistor is useful as a pass gate and as a peripheral transistor in a DRAM, and also is useful in digital and analog applications and in low power applications.

    摘要翻译： 半导体绝缘体晶体管（100）包括形成在覆盖半导体衬底（32）的绝缘层（34）上的半导体台面（36）。 第一导电类型的源区和漏区（66,68）形成在台面的相对端。 第二导电类型的体节点（56）位于台面的源极和漏极区域之间。 门绝缘体（40）和栅电极（46）位于身体节点之上。 放置光晕植入物（54,56）以将源极和漏极区域与体节点或通道区域完全分离，以改善短通道效应。 该晶体管作为通路栅极和作为DRAM中的外围晶体管是有用的，并且在数字和模拟应用以及低功率应用中也是有用的。

    Self-aligned stack formation
    5.
    发明授权
    Self-aligned stack formation 失效
    自对齐堆叠形成

    公开(公告)号：US06562724B1

    公开(公告)日：2003-05-13

    申请号：US09089795

    申请日：1998-06-03

    申请人： Steve Hsia ,  Yin Hu

    发明人： Steve Hsia ,  Yin Hu

    IPC分类号： H01L21302

    CPC分类号： H01L29/66583 ,  H01L21/28061 ,  H01L21/31116 ,  H01L21/32136 ,  H01L29/4933

    摘要： A method to simplify the polycide gate structure fabrication processes by using a hardmask 240 to define a pattern of siliciding 260 a silicon layer 230, and then using the silicide 260 to mask removal of the unreacted silicon 220 and 230 in locations where the hardmask 240 had been present. The metal silicide 260 formed in the exposed silicon regions 220 and 230 functions as a self-aligned mask against the silicon 220 and 230 etching. By using a selective etching process between the silicon 220 and 230 and the silicide 260, the silicon 220 and 230 can be etched down to the gate oxide 210 to form the polycide (silicide/polysilicon) gate. The polycide gate formed by this method is particularly advantageous in DRAM applications, but can also be used as a MOS gate in a transistor.

    摘要翻译： 一种通过使用硬掩模240来限定硅化层260的图案来硅化硅层230来简化多晶硅栅极结构制造工艺的方法，然后使用硅化物260掩盖在硬掩模240具有的位置处的未反应硅220和230的去除 已经存在 形成在暴露的硅区域220和230中的金属硅化物260用作抵抗硅220和230蚀刻的自对准掩模。 通过在硅220和230与硅化物260之间使用选择性蚀刻工艺，可将硅220和230蚀刻到栅极氧化物210以形成多晶硅化物（硅化物/多晶硅）栅极。 通过该方法形成的多晶硅栅极在DRAM应用中特别有利，但也可以用作晶体管中的MOS栅极。

    Increasing uniformity in a refill layer thickness for a semiconductor device
    6.
    发明授权
    Increasing uniformity in a refill layer thickness for a semiconductor device 失效
    增加半导体器件的补充层厚度的均匀性

    公开(公告)号：US5910017A

    公开(公告)日：1999-06-08

    申请号：US804452

    申请日：1997-02-21

    申请人： Yin Hu

    发明人： Yin Hu

    IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/31051 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283

    摘要： A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after etch back. In a silicon-on-insulator (SOI) device, dummy active areas are inserted between the active areas in order to maintain the thickness of the refill layer between the mesas to insure proper isolation between the active devices. The technique is also applicable to non-SOI devices.

    摘要翻译： 制造半导体器件或集成电路的技术产生平坦化的补充层，其在回蚀后具有更均匀的厚度。 在绝缘体上硅（SOI）器件中，在有源区之间插入虚拟有源区，以便在台面之间保持补充层的厚度，以确保有源器件之间的适当隔离。 该技术也适用于非SOI器件。

    Artificial corneal implant
    7.
    发明申请
    Artificial corneal implant 审中-公开
    人造角膜植入物

    公开(公告)号：US20110184513A1

    公开(公告)日：2011-07-28

    申请号：US12928819

    申请日：2010-12-20

    申请人： David Myung ,  Jaan Noolandi ,  Alan J. Smith ,  Curtis W. Frank ,  Christopher N. Ta ,  Yin Hu ,  Won-Gun Koh ,  Michael R. Carrasco ,  Laura Hartmann

    发明人： David Myung ,  Jaan Noolandi ,  Alan J. Smith ,  Curtis W. Frank ,  Christopher N. Ta ,  Yin Hu ,  Won-Gun Koh ,  Michael R. Carrasco ,  Laura Hartmann

    IPC分类号： A61F2/14

    CPC分类号： A61L27/3804 ,  A61F2/142 ,  A61L27/3813 ,  A61L27/3839 ,  A61L27/52 ,  A61L2430/16 ,  C12N5/0621 ,  C12N2533/30

    摘要： A material that can be applied as implants designed to artificially replace or augment the cornea, such as an artificial cornea, corneal onlay, or corneal inlay (intrastromal lens) is provided. The artificial corneal implant has a double network hydrogel with a first network interpenetrated with a second network. The first network and the second network are based on biocompatible polymers. At least one of the network polymers is based on a hydrophilic polymer. The artificial cornea or implant has epithelialization promoting biomolecules that are covalently linked to the surface of the double network hydrogel using an azide-active-ester chemical linker. Corneal epithelial cells or cornea-derived cells are adhered to the biomolecules. The double network has a physiologic diffusion coefficient to allow passage of nutrients to the adhered cells.

    摘要翻译： 提供了可以作为植入物被应用于人造地替代或增加角膜的材料，例如人造角膜，角膜镶嵌物或角膜嵌体（体内镜片）。 人造角膜植入物具有双网络水凝胶，其中第一网络与第二网络互穿。 第一个网络和第二个网络是基于生物相容的聚合物。 至少一种网状聚合物是基于亲水性聚合物。 人造角膜或植入物具有上皮促进生物分子，其使用叠氮化物 - 活性酯化学接头共价连接到双网络水凝胶的表面。 角膜上皮细胞或角膜衍生细胞粘附于生物分子。 双网络具有生理扩散系数，以允许营养物质通过粘附细胞。

    Oxide profile modification by reactant shunting
    9.
    发明授权
    Oxide profile modification by reactant shunting 有权
    通过反应物分流改性氧化物

    公开(公告)号：US06232644B1

    公开(公告)日：2001-05-15

    申请号：US09389006

    申请日：1999-09-02

    申请人： William F. Richardson ,  Yin Hu

    发明人： William F. Richardson ,  Yin Hu

    IPC分类号： H01L2900

    CPC分类号： H01L21/76202

    摘要： A method of fabricating a semiconductor device and the device which includes initially providing a layer of silicon having a thin oxide layer thereon and a patterned layer of a masking material not permeable to at least selected oxygen-bearing species and having a sidewall disposed over said oxide layer to provide an exposed intersection of the masking material and the oxide layer. An oxygen-bearing species conductive path is then formed on the sidewall of the masking material extending to the exposed intersection for conducting the selected oxygen-bearing species. A sidewall layer of a material different from the conductive path is formed on the conductive path. An oxygen-bearing species is then applied to the exposed intersection through the path and a thick oxide surrounding the masking material is fabricated concurrently or as a separate step. The masking material is preferably silicon nitride, the path is preferably silicon oxide and the sidewall layer is preferably silicon nitride.

    摘要翻译： 一种制造半导体器件的方法和该器件，其包括最初提供其上具有薄氧化物层的硅层和至少选择的含氧物质不可透过的掩模材料的图案化层，并且具有设置在所述氧化物上的侧壁 以提供掩模材料和氧化物层的暴露交叉点。 然后在掩蔽材料的侧壁上形成含氧物质导电路径，延伸到暴露的交叉点，用于导电选择的含氧物质。 在导电路径上形成不同于导电路径的材料的侧壁层。 然后将含氧物质通过路径施加到暴露的交叉点，并且围绕掩模材料的厚氧化物同时或作为单独的步骤制造。 掩模材料优选为氮化硅，该路径优选为氧化硅，并且侧壁层优选为氮化硅。

    DRAM chip fabrication method
    10.
    发明授权
    DRAM chip fabrication method 有权
    DRAM芯片制造方法

    公开(公告)号：US06207500B1

    公开(公告)日：2001-03-27

    申请号：US09140711

    申请日：1998-08-26

    申请人： Yin Hu ,  Dirk Noel Anderson

    发明人： Yin Hu ,  Dirk Noel Anderson

    IPC分类号： H01L21336

    CPC分类号： H01L27/10844 ,  H01L27/105 ,  H01L27/1052

    摘要： An improved method for forming a DRAM chip is disclosed. According to this method, a memory cell gate is deposited in a memory cell array area of the DRAM chip. The memory cell gate overlies a first channel area of a substrate. A peripheral gate is deposited in a peripheral area of the DRAM chip. The peripheral gate overlies a second channel area of the substrate. A first dopant is implanted with a first concentration in a first plurality of source and drain regions of the substrate lying predominantly outside the first and second channel areas of the substrate. A sidewall is then formed adjacent to the peripheral gate. Simultaneously, an insulating layer is formed over the memory cell array area of the DRAM chip. A second dopant is implanted with a second concentration in a second plurality of source and drain regions of the substrate within the peripheral area of the DRAM chip. The implant of the second dopant is blocked by the sidewall and the insulating layer. In one embodiment, the first and second dopants are the same, and the dopant concentration in the second plurality of regions is greater than the dopant concentration in the first plurality of regions. This method allows the formation of more heavily doped source and drain regions in the peripheral area of the DRAM chip while keeping the heavily doped regions separated from the channel regions. This reduces diffusion into the channel regions and allows a smaller design rule to be used.

    摘要翻译： 公开了一种用于形成DRAM芯片的改进方法。 根据这种方法，存储单元栅极沉积在DRAM芯片的存储单元阵列区域中。 存储单元栅极覆盖衬底的第一沟道区域。 外围栅极沉积在DRAM芯片的外围区域中。 外围栅极覆盖基板的第二通道区域。 在衬底的第一多个源极和漏极区域中以第一浓度注入第一掺杂剂，其主要位于衬底的第一和第二沟道区域的外部。 然后邻近外围栅极形成侧壁。 同时，在DRAM芯片的存储单元阵列区域上形成绝缘层。 第二掺杂剂在DRAM芯片的周边区域内的衬底的第二多个源极和漏极区域中以第二浓度注入。 第二掺杂剂的注入被侧壁和绝缘层阻挡。 在一个实施方案中，第一和第二掺杂剂相同，并且第二多个区域中的掺杂剂浓度大于第一多个区域中的掺杂剂浓度。 该方法允许在DRAM芯片的外围区域中形成更重掺杂的源极和漏极区域，同时保持重掺杂区域与沟道区域分离。 这减少了扩散到通道区域并允许使用较小的设计规则。