公开(公告)号：US07312019B2

公开(公告)日：2007-12-25

申请号：US11066495

申请日：2005-02-28

申请人： Suguru Sasaki ,  Satoshi Machida ,  Takashi Taguchi

发明人： Suguru Sasaki ,  Satoshi Machida ,  Takashi Taguchi

IPC分类号： H01L21/027

CPC分类号： G02B5/1857 ,  G03F7/0005 ,  G03F7/0035

摘要： A method of forming a linear grating is disclosed. When forming a first resist pattern covering certain surface regions of a substrate, the mask pattern position is shifted and the first resist pattern is formed such that the trench in the target region is completely filled with the first resist pattern even when an error in positioning occurs. The surface of the first resist pattern is etched, and a lower resist pattern is left to the same level as the uppermost step of the silicon substrate. On top of this, an upper resist pattern having the same pattern as the first resist pattern is formed. At this time, the mask pattern position is shifted and the exposure dose is adjusted such that one edge of the upper resist pattern is positioned on the lower resist pattern, and the other edge is positioned in a prescribed region border portion. The lower resist pattern and upper resist pattern are used as a mask to etch the silicon substrate.

摘要翻译： 公开了一种形成线性光栅的方法。 当形成覆盖基板的某些表面区域的第一抗蚀剂图案时，掩模图案位置移动，并且形成第一抗蚀剂图案，使得即使当定位错误发生时，目标区域中的沟槽也完全被第一抗蚀剂图案填充 。 蚀刻第一抗蚀剂图案的表面，并且将下抗蚀剂图案保留到与硅衬底的最上层步骤相同的水平。 此外，形成具有与第一抗蚀剂图案相同的图案的上抗蚀剂图案。 此时，掩模图案位置移动，并且调整曝光剂量使得上抗蚀剂图案的一个边缘位于下抗蚀剂图案上，另一边缘位于规定区域边界部分中。 下抗蚀剂图案和上抗蚀剂图案用作掩模以蚀刻硅衬底。

公开(公告)号：US07180199B2

公开(公告)日：2007-02-20

申请号：US11345288

申请日：2006-02-02

申请人： Satoshi Machida ,  Takashi Taguchi ,  Noboru Uchida ,  Suguru Sasaki

发明人： Satoshi Machida ,  Takashi Taguchi ,  Noboru Uchida ,  Suguru Sasaki

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a semiconductor substrate having a first surface and a second surface, and a first multilayer laminated structure film which is formed in the first surface of the semiconductor substrate and has a first layer having a first refractive index, a second layer formed on the first layer and having a second refractive index lower than the first refractive index, and a third layer formed on the second layer and having a third refractive index higher than the second refractive index, and in which the thicknesses of the respective layers are respectively thicknesses calculated by (2N+1)λ/(4n) where the wavelength of light used for detecting the first multilayer laminated structure film is defined as λ, the refractive indices of the respective layers are defined as n, and N is defined as 0 or a natural number.

摘要翻译： 半导体器件包括具有第一表面和第二表面的半导体衬底和形成在半导体衬底的第一表面中并且具有第一折射率的第一层的第一多层叠结构膜， 所述第一层具有低于所述第一折射率的第二折射率，以及形成在所述第二层上并具有高于所述第二折射率的第三折射率的第三层，并且其中各层的厚度分别为厚度 （2N + 1）λ/（4n）计算，其中将用于检测第一多层叠结构膜的光的波长定义为λ，将各层的折射率定义为n，将N定义为0或 自然数。

公开(公告)号：US20060197237A1

公开(公告)日：2006-09-07

申请号：US11345288

申请日：2006-02-02

申请人： Satoshi Machida ,  Takashi Taguchi ,  Noboru Uchida ,  Suguru Sasaki

发明人： Satoshi Machida ,  Takashi Taguchi ,  Noboru Uchida ,  Suguru Sasaki

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a semiconductor substrate having a first surface and a second surface, and a first multilayer laminated structure film which is formed in the first surface of the semiconductor substrate and has a first layer having a first refractive index, a second layer formed on the first layer and having a second refractive index lower than the first refractive index, and a third layer formed on the second layer and having a third refractive index higher than the second refractive index, and in which the thicknesses of the respective layers are respectively thicknesses calculated by (2N+1)λ/(4n) where the wavelength of light used for detecting the first multilayer laminated structure film is defined as λ, the refractive indices of the respective layers are defined as n, and N is defined as 0 or a natural number.

摘要翻译： 半导体器件包括具有第一表面和第二表面的半导体衬底和形成在半导体衬底的第一表面中并且具有第一折射率的第一层的第一多层叠结构膜， 所述第一层具有低于所述第一折射率的第二折射率，以及形成在所述第二层上并具有高于所述第二折射率的第三折射率的第三层，并且其中各层的厚度分别为厚度 （2N + 1）λ/（4n）计算，其中将用于检测第一多层叠结构膜的光的波长定义为λ，将各层的折射率定义为n，将N定义为0或 自然数。

公开(公告)号：US20050196709A1

公开(公告)日：2005-09-08

申请号：US11066495

申请日：2005-02-28

申请人： Suguru Sasaki ,  Satoshi Machida ,  Takashi Taguchi

发明人： Suguru Sasaki ,  Satoshi Machida ,  Takashi Taguchi

IPC分类号： G02B5/18

CPC分类号： G02B5/1857 ,  G03F7/0005 ,  G03F7/0035

摘要： A method of forming a linear grating is disclosed. When forming a first resist pattern covering certain surface regions of a substrate, the mask pattern position is shifted and the first resist pattern is formed such that the trench in the target region is completely filled with the first resist pattern even when an error in positioning occurs. The surface of the first resist pattern is etched, and a lower resist pattern is left to the same level as the uppermost step of the silicon substrate. On top of this, an upper resist pattern having the same pattern as the first resist pattern is formed. At this time, the mask pattern position is shifted and the exposure dose is adjusted such that one edge of the upper resist pattern is positioned on the lower resist pattern, and the other edge is positioned in a prescribed region border portion. The lower resist pattern and upper resist pattern are used as a mask to etch the silicon substrate.

摘要翻译： 公开了一种形成线性光栅的方法。 当形成覆盖基板的某些表面区域的第一抗蚀剂图案时，掩模图案位置移动，并且形成第一抗蚀剂图案，使得即使当定位错误发生时，目标区域中的沟槽也完全被第一抗蚀剂图案填充 。 蚀刻第一抗蚀剂图案的表面，并且将下抗蚀剂图案保留到与硅衬底的最上层步骤相同的水平。 此外，形成具有与第一抗蚀剂图案相同的图案的上抗蚀剂图案。 此时，掩模图案位置移动，并且调整曝光剂量使得上抗蚀剂图案的一个边缘位于下抗蚀剂图案上，另一边缘位于规定区域边界部分中。 下抗蚀剂图案和上抗蚀剂图案用作掩模以蚀刻硅衬底。

公开(公告)号：US08310068B2

公开(公告)日：2012-11-13

申请号：US12805017

申请日：2010-07-07

申请人： Suguru Sasaki

发明人： Suguru Sasaki

IPC分类号： H01L23/08 ,  H01L23/48 ,  H01L31/26

CPC分类号： H01L23/4985 ,  H01L2924/0002 ,  H01L2924/00

摘要： A TCP type semiconductor device, which is connected to a plurality of substrate-side electrodes parallel to each other and each having a linear shape, has: a base film; a semiconductor chip mounted on the base film; and a plurality of leads formed on the base film and electrically connecting between the semiconductor chip and the plurality of substrate-side electrodes, respectively. Each of the plurality of leads has an external terminal section extending in a first direction and configured to come in contact with corresponding one of the plurality of substrate-side electrodes. A part of the external terminal section is a wide section that is formed wider than the other section of the external terminal section A position of the wide section in the first direction is different between adjacent leads of the plurality of leads.

摘要翻译： 连接到彼此平行并且各自具有直线形状的多个基板侧电极的TCP型半导体器件具有：基膜; 安装在基膜上的半导体芯片; 以及形成在所述基膜上并分别电连接所述半导体芯片和所述多个基板侧电极的多个引线。 所述多个引线中的每一个具有沿第一方向延伸的外部端子部，并且被配置为与所述多个基板侧电极中的相应一个电极接触。 外部端子部分的一部分是形成为比外部端子部分A的另一部分宽的宽部分。在多个引线的相邻引线之间，第一方向上的宽部分的位置不同。

公开(公告)号：US07459243B2

公开(公告)日：2008-12-02

申请号：US10942034

申请日：2004-09-16

申请人： Suguru Sasaki

发明人： Suguru Sasaki

IPC分类号： G03F1/00

CPC分类号： G03F1/36

摘要： A mask pattern correcting method is comprised of a before-correction pattern edge defining step for defining an edge of a mask pattern, a deviated position setting step for setting a close point and a isolated point based on the deviation between the pattern edges of the mask pattern and the design pattern, an edge selecting step for correcting an edge located within specified distance from the isolated point, and selecting a mask pattern edge that will have smaller variation of the close point light intensity and larger variation of isolated point light intensity by the correction, a correcting step for correcting an edge to be corrected such that the isolated point light intensity after correction satisfies a criterion for correction, an after-correction pattern edge defining step for defining a pattern edge of the corrected mask pattern, and an end determining step for ending correction when the deviation between the defined after-correction pattern edge and the edge of the design pattern is within a specified criteria for determining ending correction.

摘要翻译： 掩模图案校正方法包括用于限定掩模图案的边缘的前校正图案边缘限定步骤，基于掩模的图案边缘之间的偏差设置接近点和隔离点的偏离位置设置步骤 图案和设计图案，边缘选择步骤，用于校正位于距离孤立点的指定距离内的边缘，并且选择将具有较小的近点光强变化和孤立点光强度变化较小的掩模图案边缘， 校正步骤，用于校正要校正的边缘，使得校正后的孤立点光强度满足校正标准;修正后图案边缘定义步骤，用于定义校正的掩模图案的图案边缘;以及结束确定 当定义的校正后图案边缘与设计边缘之间的偏差p时，用于结束校正的步骤 attern在确定结束修正的指定标准之内。

公开(公告)号：US08890561B2

公开(公告)日：2014-11-18

申请号：US13365508

申请日：2012-02-03

申请人： Suguru Sasaki

发明人： Suguru Sasaki

IPC分类号： G01R31/26 ,  H01L23/495 ,  G01R31/28 ,  H01L23/00

CPC分类号： G01R31/2884 ,  H01L24/50 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014

摘要： A semiconductor device includes a base film, a semiconductor chip mounted on the base film, and a plurality of leads formed on the base film, each of the leads including one end coupled to the semiconductor chip and another end being opposite to the one end. The another end of a first one of the leads and the another end of a second one of the leads are located at different positions respectively between the semiconductor chip and a cut line along which the base film is cut.

摘要翻译： 半导体器件包括基膜，安装在基膜上的半导体芯片和形成在基膜上的多个引线，每个引线包括一端连接到半导体芯片，另一端与该一端相对。 引线中的第一个引线的另一端和第二引线的另一端分别位于半导体芯片与切割基片之间的切割线之间的不同位置处。

公开(公告)号：US20110049688A1

公开(公告)日：2011-03-03

申请号：US12805017

申请日：2010-07-07

申请人： Suguru Sasaki

发明人： Suguru Sasaki

IPC分类号： H01L23/495

CPC分类号： H01L23/4985 ,  H01L2924/0002 ,  H01L2924/00

摘要： A TCP type semiconductor device, which is connected to a plurality of substrate-side electrodes parallel to each other and each having a linear shape, has: a base film; a semiconductor chip mounted on the base film; and a plurality of leads formed on the base film and electrically connecting between the semiconductor chip and the plurality of substrate-side electrodes, respectively. Each of the plurality of leads has an external terminal section extending in a first direction and configured to come in contact with corresponding one of the plurality of substrate-side electrodes. A part of the external terminal section is a wide section that is formed wider than the other section of the external terminal section A position of the wide section in the first direction is different between adjacent leads of the plurality of leads.

摘要翻译： 连接到彼此平行并且各自具有直线形状的多个基板侧电极的TCP型半导体器件具有：基膜; 安装在基膜上的半导体芯片; 以及形成在所述基膜上并分别电连接所述半导体芯片和所述多个基板侧电极的多个引线。 所述多个引线中的每一个具有沿第一方向延伸的外部端子部，并且被配置为与所述多个基板侧电极中的相应一个电极接触。 外部端子部分的一部分是形成为比外部端子部分A的另一部分宽的宽部分。在多个引线的相邻引线之间，第一方向上的宽部分的位置不同。

公开(公告)号：US20050136339A1

公开(公告)日：2005-06-23

申请号：US10942034

申请日：2004-09-16

申请人： Suguru Sasaki

发明人： Suguru Sasaki

IPC分类号： G03C3/02 ,  G03C5/00 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F9/00 ,  G06F17/50

CPC分类号： G03F1/36

摘要： A mask pattern correcting method is comprised of a before-correction pattern edge defining step for defining an edge of a mask pattern, a deviated position setting step for setting a close point and a isolated point based on the deviation between the pattern edges of the mask pattern and the design pattern, an edge selecting step for correcting an edge located within specified distance from the isolated point, and selecting a mask pattern edge that will have smaller variation of the close point light intensity and larger variation of isolated point light intensity by the correction, a correcting step for correcting an edge to be corrected such that the isolated point light intensity after correction satisfies a criterion for correction, an after-correction pattern edge defining step for defining a pattern edge of the corrected mask pattern, and an end determining step for ending correction when the deviation between the defined after-correction pattern edge and the edge of the design pattern is within a specified criteria for determining ending correction.

摘要翻译： 掩模图案校正方法包括用于限定掩模图案的边缘的前校正图案边缘限定步骤，基于掩模的图案边缘之间的偏差设置接近点和隔离点的偏离位置设置步骤 图案和设计图案，边缘选择步骤，用于校正位于距离孤立点的指定距离内的边缘，并且选择将具有较小的近点光强变化和孤立点光强度变化较小的掩模图案边缘， 校正步骤，用于校正要校正的边缘，使得校正后的孤立点光强度满足校正标准;修正后图案边缘定义步骤，用于定义校正的掩模图案的图案边缘;以及结束确定 当定义的校正后图案边缘与设计边缘之间的偏差p时，用于结束校正的步骤 attern在确定结束修正的指定标准之内。

公开(公告)号：US20100109690A1

公开(公告)日：2010-05-06

申请号：US12588460

申请日：2009-10-15

申请人： Suguru Sasaki

发明人： Suguru Sasaki

IPC分类号： G01R31/02 ,  H01L23/495

CPC分类号： G01R31/2884 ,  H01L24/50 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014

摘要： A TCP-type semiconductor device has: a base film; a semiconductor chip mounted on the base film; and a plurality of leads formed on the base film. Each lead has: a first terminal portion including a first end that is one end of the each lead and connected to the semiconductor chip; and a second terminal portion including a second end that is the other end of the each lead and located on the opposite side of the first terminal portion. I a terminal region including the second terminal portion of the each lead, the plurality of leads are parallel to each other along a first direction, the plurality of leads include a first lead and a second lead that are adjacent to each other, and the first lead and the second lead are different in a position of the second end in the first direction.

摘要翻译： TCP型半导体器件具有：基膜; 安装在基膜上的半导体芯片; 以及形成在基膜上的多个引线。 每个引线具有：第一端子部分，其包括作为每个引线的一端并连接到半导体芯片的第一端; 以及第二端子部分，其包括作为每个引线的另一端并位于第一端子部分的相对侧上的第二端。 一个包括每个引线的第二端子部分的端子区域，多个引线沿着第一方向彼此平行，多个引线包括彼此相邻的第一引线和第二引线，第一引线 引线和第二引线在第二方向的第二端的位置不同。