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公开(公告)号：US09026769B1
公开(公告)日：2015-05-05
申请号：US13357567
申请日：2012-01-24
CPC分类号： G06F9/3855 , G06F9/325 , G06F9/381 , G06F9/3836
摘要： A processor for processing loop instructions can include an instruction reorder structure and a loop processing controller. The instruction reorder structure is configured to store decoded instructions according to program order and issue the decoded instructions for execution out of program order. The loop processing controller is configured to detect a loop in the decoded instructions stored in the instruction reorder structure and cause the instruction reorder structure to reissue the decoded instructions that form the loop for re-execution.
摘要翻译： 用于处理循环指令的处理器可以包括指令重排序结构和循环处理控制器。 指令重排结构被配置为根据程序顺序存储解码指令，并发出解码指令以执行程序顺序。 循环处理控制器被配置为检测存储在指令重排序结构中的解码指令中的循环，并使指令重排序结构重新发出构成循环的解码指令以便重新执行。
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公开(公告)号：US08943273B1
公开(公告)日：2015-01-27
申请号：US12541277
申请日：2009-08-14
申请人： Sujat Jamil , R. Frank O'Bleness , Russell Robideau , Tom Hameenanttila , Joseph Delgross , David Miner
发明人： Sujat Jamil , R. Frank O'Bleness , Russell Robideau , Tom Hameenanttila , Joseph Delgross , David Miner
IPC分类号： G06F9/38
CPC分类号： G06F12/0875 , G06F9/30043 , G06F9/3826 , G06F9/3842 , G06F9/3859 , G06F12/0804 , G06F2212/452
摘要： Aspects of the disclosure provide methods for cache efficiency. A method for cache efficiency can include storing data in a buffer entry in association with a cache array in response to a first store instruction that hits the cache array before the first store instruction is committed. Further, when a dependent load instruction is subsequent to the first store instruction, the method can include providing the data from the buffer entry in response to the first dependent load instruction. When a second store instruction overlaps an address of the first store instruction, the method can include coalescing data of the second store instruction in the buffer entry before the second store instruction is committed. When the second store instruction is followed by a second dependent load instruction, the method can include providing the coalesced data from the buffer entry in response to the second dependent load instruction.
摘要翻译： 本公开的方面提供了缓存效率的方法。 一种用于高速缓存效率的方法可以包括：响应于第一个存储指令在第一个存储指令被提交之前触发高速缓冲存储器阵列，将数据与高速缓冲存储器阵列相关联地存储在缓冲器条目中。 此外，当依赖加载指令在第一存储指令之后时，该方法可以包括响应于第一依赖加载指令从缓冲器条目提供数据。 当第二存储指令与第一存储指令的地址重叠时，该方法可以包括在提交第二存储指令之前将缓冲器条目中的第二存储指令的数据合并。 当第二存储指令后跟第二相关加载指令时，该方法可以包括响应于第二依赖加载指令从缓冲器条目提供合并的数据。
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3.发明授权Programmable cache access protocol to optimize power consumption and performance 有权可编程缓存访问协议，以优化功耗和性能公开(公告)号：US08458404B1
公开(公告)日：2013-06-04
申请号：US12540788
申请日：2009-08-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F2212/502 , G06F2212/601 , Y02D10/13
摘要： A programmable cache and cache access protocol that can be dynamically optimized with respect to either power consumption or performance based on a monitored performance of the cache. A monitoring unit monitors cache misses, load use penalty, and/or other performance parameter, and compares the monitored values against a set of one or more predetermined thresholds. Based on the comparison results, a cache controller configures the programmable cache to operate in a parallel mode, to increase cache performance at the cost of greater power consumption, or in a serial mode, to conserve power at the cost of unnecessary performance. A banked cache memory that supports aligned and unaligned instruction fetches using a banked access strategy, and a cache access controller that includes a prefetch capability are also described.
摘要翻译： 可编程高速缓存和缓存访问协议，可根据高速缓存的受监控性能，针对功耗或性能进行动态优化。 监视单元监视高速缓存未命中，加载使用罚分和/或其他性能参数，并将所监视的值与一组或多个预定阈值进行比较。 基于比较结果，高速缓存控制器将可编程高速缓存器配置为以并行模式操作，以牺牲更大功耗或串行模式为代价来增加高速缓存性能，从而以不必要的性能为代价来节省功耗。 还描述了一种使用库存访问策略来支持对齐和未对齐指令取出的存储缓存，并且还描述了包括预取能力的高速缓存访问控制器。
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4.发明授权Method and apparatus for hardware-configurable multi-policy coherence protocol 有权用于硬件可配置的多策略一致性协议的方法和装置公开(公告)号：US08135916B1
公开(公告)日：2012-03-13
申请号：US12416359
申请日：2009-04-01
申请人： R. Frank O'Bleness , Sujat Jamil , David E. Miner , Joseph Delgross , Tom Hameenanttila , Jeffrey Kehl
发明人： R. Frank O'Bleness , Sujat Jamil , David E. Miner , Joseph Delgross , Tom Hameenanttila , Jeffrey Kehl
CPC分类号： G06F12/0815 , G06F2212/601
摘要： A processor includes a first level of cache memory and a first set of instructions configured to implement a first cache coherency protocol. The processor also includes a second set of instructions configured to implement a second cache coherency protocol and a cache coherency protocol selector having at least two choice-states. The processor further includes a cache coherency implementer configured to implement the first cache coherency protocol or the second cache coherency with respect to the first level of cache memory based on a selected choice-state of the cache coherency protocol selector.
摘要翻译： 处理器包括第一级缓存存储器和被配置为实现第一高速缓存一致性协议的第一组指令。 处理器还包括被配置为实现第二高速缓存一致性协议的第二组指令和具有至少两个选择状态的高速缓存一致性协议选择器。 处理器还包括缓存一致性实现器，其被配置为基于所选择的高速缓存一致性协议选择器的选择状态来相对于高速缓冲存储器的第一级实现第一高速缓存一致性协议或第二高速缓存一致性。
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公开(公告)号：US08990505B1
公开(公告)日：2015-03-24
申请号：US12235251
申请日：2008-09-22
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0864 , G06F12/0871 , G06F2212/1016 , G06F2212/1028 , G06F2212/502 , G06F2212/6082 , Y02D10/13
摘要： Devices, systems, methods, and other embodiments associated with a cache memory are described. In one embodiment, a cache tag array includes tag banks. The cache memory further includes a bank selector configured to receive an address and to apply a hash function that maps the address to one of the tag banks.
摘要翻译： 描述了与高速缓冲存储器相关联的设备，系统，方法和其他实施例。 在一个实施例中，高速缓存标签阵列包括标签库。 高速缓冲存储器还包括配置成接收地址并且应用将地址映射到标签组之一的散列函数的存储体选择器。
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公开(公告)号：US08631206B1
公开(公告)日：2014-01-14
申请号：US12194841
申请日：2008-08-20
CPC分类号： G06F12/1054 , G06F12/0864 , Y02D10/13
摘要： Set-associative caches having corresponding methods and computer programs comprise: a data cache to provide a plurality of cache lines based on a set index of a virtual address, wherein each of the cache lines corresponds to one of a plurality of ways of the set-associative cache; a translation lookaside buffer to provide one of a plurality of way selections based on the set index of the virtual address and a virtual tag of the virtual address, wherein each of the way selections corresponds to one of the ways of the set-associative cache; and a way multiplexer to select one of the cache lines provided by the data cache based on the one of the plurality of way selections.
摘要翻译： 具有相应方法和计算机程序的组合关联高速缓存包括：数据高速缓存，用于基于虚拟地址的设置索引提供多条高速缓存行，其中每条高速缓存行对应于设置的多个方式中的一个， 关联缓存; 翻译后备缓冲器，用于基于所述虚拟地址的所述设置索引和所述虚拟地址的虚拟标签提供多种方式选择之一，其中所述方式选择中的每一种对应于所述集合关联高速缓存的方式之一; 以及方式多路复用器，用于基于多路选择中的一种选择来选择由数据高速缓存提供的高速缓存行之一。
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