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    Three-dimensional memory string array of thin-film ferroelectric transistors
    2.
    发明授权
    Three-dimensional memory string array of thin-film ferroelectric transistors 有权

    公开(公告)号：US12160996B2

    公开(公告)日：2024-12-03

    申请号：US18483322

    申请日：2023-10-09

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Christopher J. Petti ,  Vinod Purayath ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

    IPC: H10B51/30 ,  G11C11/22 ,  H10B51/20

    Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

    QUASI-VOLATILE MEMORY WITH REFERENCE BIT LINE STRUCTURE
    6.
    发明申请
    QUASI-VOLATILE MEMORY WITH REFERENCE BIT LINE STRUCTURE 有权

    公开(公告)号：US20220238551A1

    公开(公告)日：2022-07-28

    申请号：US17576416

    申请日：2022-01-14

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Christopher J. Petti

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11597 ,  H01L27/11592 ,  G11C16/26 ,  G11C11/22

    Abstract: A semiconductor memory device is implemented as strings of storage transistors, where the storage transistors in each string have drain terminals connected to a bit line and gate terminals connected to respective word lines. In some embodiments, the semiconductor memory device includes a reference bit line structure to provide a reference bit line signal for read operation. The reference bit line structure configures word line connections to provide a reference bit line to be used with a storage transistor being selected for read access. The reference bit line structure provides a reference bit line having the same electrical characteristics as an active bit line and is configured so that no storage transistors are selected when a word line is activated to access a selected storage transistor associated with the active bit line.

    THREE-DIMENSIONAL NOR MEMORY STRING ARRAYS OF THIN-FILM FERROELECTRIC TRANSISTORS
    8.
    发明申请
    THREE-DIMENSIONAL NOR MEMORY STRING ARRAYS OF THIN-FILM FERROELECTRIC TRANSISTORS 有权

    公开(公告)号：US20230077181A1

    公开(公告)日：2023-03-09

    申请号：US17817609

    申请日：2022-08-04

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Christopher J. Petti ,  Eli Harari

    IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/04 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78

    Abstract: A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent a semiconductor channel. In some embodiments, the semiconductor channel is formed by an oxide semiconductor material and the ferroelectric storage transistors are junctionless transistors with no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a first conductive layer as a common source line and a second conductive layer as a common bit line, the first and second conductive layers being in electrical contact with the semiconductor channel. The ferroelectric storage transistors in a multiplicity of NOR memory strings are arranged to form semi-autonomous three-dimensional memory arrays (tiles) with each tile individually addressed and controlled by circuitry in the semiconductor substrate underneath each tile in cooperation with a memory controller.

    SEMICONDUCTOR MEMORY DEVICE WITH WRITE DISTURB REDUCTION
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WITH WRITE DISTURB REDUCTION 有权

    公开(公告)号：US20220293188A1

    公开(公告)日：2022-09-15

    申请号：US17685133

    申请日：2022-03-02

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Christopher J. Petti

    IPC: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24

    Abstract: A semiconductor memory device implements a write disturb reduction method to reduce write disturb on unselected memory cells by alternating the order of the write logical “1” step and write logical “0” step in the write operations of selected memory cells associated with the same group of bit lines. In one embodiment, a method in an array of memory cells includes performing write operation on the memory cells in one of the memory pages to store write data into the memory cells where the write operation includes a first write step of writing a data of a first logical state and a second write step of writing data of a second logical state; and performing the write operation for each row of memory cells by alternately performing the first write step followed by the second write step and performing the second write step followed by the first write step.

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