公开(公告)号：US20110049592A1

公开(公告)日：2011-03-03

申请号：US12838878

申请日：2010-07-19

申请人： Sung Min YOON ,  Chun Won BYUN ,  Shin Hyuk YANG ,  Sang Hee PARK ,  Soon Won JUNG ,  Seung Youl KANG ,  Chi Sun HWANG ,  Byoung Gon YUN

发明人： Sung Min YOON ,  Chun Won BYUN ,  Shin Hyuk YANG ,  Sang Hee PARK ,  Soon Won JUNG ,  Seung Youl KANG ,  Chi Sun HWANG ,  Byoung Gon YUN

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/6684 ,  B82Y10/00 ,  G11C11/22 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/78391

摘要： Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.

摘要翻译： 提供一种非易失性存储单元及其制造方法。 非易失性存储单元包括存储晶体管和驱动晶体管。 存储晶体管包括设置在基板上的半导体层，缓冲层，有机铁电层和栅极电极。 驱动晶体管包括设置在基板上的半导体层，缓冲层，栅极绝缘层和栅极电极。 存储晶体管和驱动晶体管设置在同一衬底上。 非易失性存储单元在可见光区域是透明的。

公开(公告)号：US20110305062A1

公开(公告)日：2011-12-15

申请号：US12887316

申请日：2010-09-21

申请人： Chun Won BYUN ,  Byeong Hoon Kim ,  Sung Min Yoon ,  Kyoung Ik Cho ,  Sang Hee Park ,  Chi Sun Hwang ,  Min Ki Ryu ,  Shin Hyuk Yang ,  Oh Sang Kwon ,  Eun Suk Park

发明人： Chun Won BYUN ,  Byeong Hoon Kim ,  Sung Min Yoon ,  Kyoung Ik Cho ,  Sang Hee Park ,  Chi Sun Hwang ,  Min Ki Ryu ,  Shin Hyuk Yang ,  Oh Sang Kwon ,  Eun Suk Park

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Provided are a memory cell and a memory device using the same, particularly, a nonvolatile non-destructive readable random access memory cell including a ferroelectric transistor as a storage unit and a memory device using the same. The memory cell includes a ferroelectric transistor having a drain to which a reference voltage is applied, a first switch configured to allow a source of the ferroelectric transistor to be connected to a first line in response to a scan signal, and a second switch configured to allow a gate of the ferroelectric transistor to be connected to a second line in response to the scan signal. The memory device enables random access and performs non-destructive read-out (NDRO) operations.

摘要翻译： 提供了一种存储器单元和使用该存储单元的存储器件，特别地，包括作为存储单元的铁电晶体管的非易失性非破坏性可读随机存取存储单元和使用该存储单元的存储器件。 存储单元包括具有施加了参考电压的漏极的铁电晶体管，被配置为允许铁电晶体管的源被响应于扫描信号连接到第一线的第一开关，以及被配置为 允许铁电晶体管的栅极响应于扫描信号连接到第二线。 存储器件允许随机访问并执行非破坏性读出（NDRO）操作。

公开(公告)号：US20130214299A1

公开(公告)日：2013-08-22

申请号：US13618308

申请日：2012-09-14

申请人： Hye Young RYU ,  Hee Jun BYEON ,  Woo Geun LEE ,  Kap Soo YOON ,  Yoon Ho KIM ,  Chun Won BYUN

发明人： Hye Young RYU ,  Hee Jun BYEON ,  Woo Geun LEE ,  Kap Soo YOON ,  Yoon Ho KIM ,  Chun Won BYUN

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/127 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2001/136295 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262

摘要： A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.

摘要翻译： 根据本发明的示例性实施例的薄膜晶体管阵列面板及其制造方法在由有机绝缘体形成的第二钝化层中形成接触孔，通过用由保护构件形成的保护构件覆盖来保护接触孔的一侧 与第一场产生电极相同的层并由透明导电材料形成，并且使用保护构件作为掩模，将第二钝化层下面的第一钝化层蚀刻。 因此，可以防止由有机绝缘体形成的第二钝化层在蚀刻第二钝化层下方的绝缘层的同时进行过蚀刻，从而防止接触孔过宽。