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    Transparent transistor with multi-layered structures and method of manufacturing the same
    1.
    发明授权
    Transparent transistor with multi-layered structures and method of manufacturing the same 有权
    具有多层结构的透明晶体管及其制造方法

    公开(公告)号：US08269220B2

    公开(公告)日：2012-09-18

    申请号：US12554066

    申请日：2009-09-04

    申请人： Min Ki Ryu ,  Chi Sun Hwang ,  Chun Won Byun ,  Hye Yong Chu ,  Kyoung Ik Cho

    发明人： Min Ki Ryu ,  Chi Sun Hwang ,  Chun Won Byun ,  Hye Yong Chu ,  Kyoung Ik Cho

    IPC分类号： H01L29/04

    CPC分类号： H01L29/66742 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/7869

    摘要： Provided is a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. Here, the lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel. Thus, the use of the multi-layered transparent conductive layer can ensure transparency and conductivity, overcome a problem of contact resistance between the source and drain electrodes and a semiconductor, and improve processibility by patterning the multi-layered transparent conductive layer all at once, while deposition is performed layer by layer.

    摘要翻译： 提供了一种透明晶体管，其包括形成在基板上的基板，源电极和漏电极，每个具有下透明层，金属层和上透明层的多层结构，在源极和漏极之间形成的沟道， 以及与沟道对准的栅电极。 这里，下透明层或上透明层由与通道相同的透明半导体层形成。 因此，使用多层透明导电层可以确保透明性和导电性，克服了源极和漏极之间的接触电阻和半导体的问题，并且通过一次构图多层透明导电层来提高加工性， 同时逐层进行沉积。

    MEMORY CELL AND MEMORY DEVICE USING THE SAME
    2.
    发明申请
    MEMORY CELL AND MEMORY DEVICE USING THE SAME 审中-公开
    使用该存储单元的存储单元和存储器件

    公开(公告)号：US20110305062A1

    公开(公告)日：2011-12-15

    申请号：US12887316

    申请日：2010-09-21

    申请人： Chun Won BYUN ,  Byeong Hoon Kim ,  Sung Min Yoon ,  Kyoung Ik Cho ,  Sang Hee Park ,  Chi Sun Hwang ,  Min Ki Ryu ,  Shin Hyuk Yang ,  Oh Sang Kwon ,  Eun Suk Park

    发明人： Chun Won BYUN ,  Byeong Hoon Kim ,  Sung Min Yoon ,  Kyoung Ik Cho ,  Sang Hee Park ,  Chi Sun Hwang ,  Min Ki Ryu ,  Shin Hyuk Yang ,  Oh Sang Kwon ,  Eun Suk Park

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22

    摘要： Provided are a memory cell and a memory device using the same, particularly, a nonvolatile non-destructive readable random access memory cell including a ferroelectric transistor as a storage unit and a memory device using the same. The memory cell includes a ferroelectric transistor having a drain to which a reference voltage is applied, a first switch configured to allow a source of the ferroelectric transistor to be connected to a first line in response to a scan signal, and a second switch configured to allow a gate of the ferroelectric transistor to be connected to a second line in response to the scan signal. The memory device enables random access and performs non-destructive read-out (NDRO) operations.

    摘要翻译： 提供了一种存储器单元和使用该存储单元的存储器件，特别地，包括作为存储单元的铁电晶体管的非易失性非破坏性可读随机存取存储单元和使用该存储单元的存储器件。 存储单元包括具有施加了参考电压的漏极的铁电晶体管，被配置为允许铁电晶体管的源被响应于扫描信号连接到第一线的第一开关，以及被配置为 允许铁电晶体管的栅极响应于扫描信号连接到第二线。 存储器件允许随机访问并执行非破坏性读出（NDRO）操作。

    TRANSPARENT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    TRANSPARENT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
    透明晶体管及其制造方法

    公开(公告)号：US20100155792A1

    公开(公告)日：2010-06-24

    申请号：US12554066

    申请日：2009-09-04

    申请人： Min Ki Ryu ,  Chi Sun Hwang ,  Chun Won Byun ,  Hye Yong Chu ,  Kyong Ik Cho

    发明人： Min Ki Ryu ,  Chi Sun Hwang ,  Chun Won Byun ,  Hye Yong Chu ,  Kyong Ik Cho

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66742 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/7869

    摘要： Provided is a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. Here, the lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel. Thus, the use of the multi-layered transparent conductive layer can ensure transparency and conductivity, overcome a problem of contact resistance between the source and drain electrodes and a semiconductor, and improve processibility by patterning the multi-layered transparent conductive layer all at once, while deposition is performed layer by layer.

    摘要翻译： 提供了一种透明晶体管，其包括形成在基板上的基板，源电极和漏电极，每个具有下透明层，金属层和上透明层的多层结构，在源极和漏极之间形成的沟道， 以及与沟道对准的栅电极。 这里，下透明层或上透明层由与通道相同的透明半导体层形成。 因此，使用多层透明导电层可以确保透明性和导电性，克服了源极和漏极之间的接触电阻和半导体的问题，并且通过一次构图多层透明导电层来提高加工性， 同时逐层进行沉积。

    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管阵列及其制造方法

    公开(公告)号：US20130214299A1

    公开(公告)日：2013-08-22

    申请号：US13618308

    申请日：2012-09-14

    申请人： Hye Young RYU ,  Hee Jun BYEON ,  Woo Geun LEE ,  Kap Soo YOON ,  Yoon Ho KIM ,  Chun Won BYUN

    发明人： Hye Young RYU ,  Hee Jun BYEON ,  Woo Geun LEE ,  Kap Soo YOON ,  Yoon Ho KIM ,  Chun Won BYUN

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L27/127 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2001/136295 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262

    摘要： A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.

    摘要翻译： 根据本发明的示例性实施例的薄膜晶体管阵列面板及其制造方法在由有机绝缘体形成的第二钝化层中形成接触孔，通过用由保护构件形成的保护构件覆盖来保护接触孔的一侧 与第一场产生电极相同的层并由透明导电材料形成，并且使用保护构件作为掩模，将第二钝化层下面的第一钝化层蚀刻。 因此，可以防止由有机绝缘体形成的第二钝化层在蚀刻第二钝化层下方的绝缘层的同时进行过蚀刻，从而防止接触孔过宽。

    NON-VOLATILE MEMORY TRANSISTOR HAVING DOUBLE GATE STRUCTURE
    9.
    发明申请
    NON-VOLATILE MEMORY TRANSISTOR HAVING DOUBLE GATE STRUCTURE 审中-公开
    具有双门结构的非易失性存储器晶体管

    公开(公告)号：US20120007158A1

    公开(公告)日：2012-01-12

    申请号：US13173625

    申请日：2011-06-30

    申请人： Sung Min YOON ,  Shin Hyuk Yang ,  Chun Won Byun ,  Min Ki Ryu ,  Soon Won Jung

    发明人： Sung Min YOON ,  Shin Hyuk Yang ,  Chun Won Byun ,  Min Ki Ryu ,  Soon Won Jung

    IPC分类号： H01L27/088

    CPC分类号： H01L29/78391 ,  H01L29/22 ,  H01L29/40111 ,  H01L29/516

    摘要： Provided is a non-volatile memory transistor having a double gate structure, including a first gate electrode formed on a substrate and to which an operating voltage is applied, a first gate insulating layer formed on the first gate electrode, source and drain electrodes formed on the first gate insulating layer at predetermined intervals, a channel layer formed on the first gate insulating layer between the source and drain electrodes, a second gate insulating layer formed on the channel layer, and a second gate electrode formed on the second gate insulating layer and connected to the first gate electrode such that the operating voltage is applied thereto. Accordingly, a turn-on voltage of the memory transistor can be easily controlled.

    摘要翻译： 本发明提供一种具有双栅极结构的非易失性存储晶体管，包括形成于基板上的第一栅电极，施加工作电压的第一栅极绝缘层，形成在第一栅电极上的源电极和漏电极， 所述第一栅极绝缘层以预定间隔形成，沟道层，形成在所述源极和漏极之间的所述第一栅极绝缘层上，形成在所述沟道层上的第二栅极绝缘层，以及形成在所述第二栅极绝缘层上的第二栅极电极， 连接到第一栅电极，使得施加工作电压。 因此，可以容易地控制存储晶体管的接通电压。