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    Non-volatile memory device and method of fabricating the same
    1.
    发明授权
    Non-volatile memory device and method of fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US07511998B2

    公开(公告)日：2009-03-31

    申请号：US11803425

    申请日：2007-05-15

    申请人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Dong-Gun Park ,  Eun-Jung Yun

    发明人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Dong-Gun Park ,  Eun-Jung Yun

    IPC分类号： G11C16/04

    CPC分类号： H01L27/101 ,  H01L27/24

    摘要： A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device. In one embodiment, a non-volatile memory device comprises a first word line and a second word line insulated from each other and positioned to intersect each other with a vacant space therebetween; a bit line in the vacant space between one of the first word line and the second word line and positioned in parallel with one of the first word line and the second word line, the bit line constructed and arranged to be deflected toward one of the first word line and the second word line by an electric field induced between the first word line and the second word line; and a trap site between the bit line and one of the first word line and the second word line intersecting the bit line, the trap site being insulated from the one of the first word line and the second word line intersecting the bit line and spaced apart from the bit line by a portion of the vacant space, the trap site configured to trap a predetermined electric charge to electrostatically fix the bit line in a deflected position in the direction of the one of the word lines.

    摘要翻译： 非易失性存储器件及其形成方法增加或最大化超微结构器件的性能。 在一个实施例中，非易失性存储器件包括第一字线和第二字线，该第一字线和第二字线彼此绝缘并且被定位成彼此相交并具有空隙; 位于第一字线和第二字线中的一个之间的空白空间中的位线，并且与第一字线和第二字线之一平行地定位，位线被构造和布置成朝向第一字线 字线和第二字线由在第一字线和第二字线之间感应的电场; 位线与位线相交的第一字线和第二字线之一之间的陷阱位置，陷阱位置与第一字线和第二字线之一绝缘，与位线相交并间隔开 从位线通过空闲空间的一部分，陷阱位置被配置为捕获预定电荷以将位线静电地固定在一条字线的方向上的偏转位置。

    Method of fabricating a multi-bit electro-mechanical memory device
    2.
    发明授权
    Method of fabricating a multi-bit electro-mechanical memory device 有权
    制造多位机电存储器件的方法

    公开(公告)号：US07790494B2

    公开(公告)日：2010-09-07

    申请号：US12007819

    申请日：2008-01-16

    申请人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

    发明人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

    IPC分类号： H01L21/00 ,  H01L35/24 ,  H01L51/00 ,  H01L29/792

    CPC分类号： G11C11/56 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/16 ,  H01L29/0665 ,  H01L29/0673

    摘要： A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.

    摘要翻译： 存储器件可以包括衬底，位线，至少第一下部字线，至少第一陷阱位置，焊盘电极，至少第一悬臂电极和/或至少第一上部字线。 位线可以在第一方向上形成在基板上。 第一下部字线和第一陷阱位置可以与位线绝缘并且沿与该位线交叉的第二方向形成。 焊盘电极可以在第一下字线和第一陷阱位置的侧壁处绝缘并连接到位线。 第一悬臂电极可以形成在第一方向上，连接到焊盘电极，浮在第一陷阱位置上，具有至少第一下部空的空间，和/或构造成沿第三方向弯曲。 第一上部字线可以在第二方向上的第一悬臂电极上形成有至少第一上部空置空间。

    Multi-bit electro-mechanical memory device and method of manufacturing the same
    3.
    发明授权
    Multi-bit electro-mechanical memory device and method of manufacturing the same 失效
    多位机电记忆体装置及其制造方法

    公开(公告)号：US07719068B2

    公开(公告)日：2010-05-18

    申请号：US12002668

    申请日：2007-12-18

    申请人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-Jung Yun ,  Dong-Gun Park

    发明人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-Jung Yun ,  Dong-Gun Park

    IPC分类号： G11C11/50

    CPC分类号： H01L29/788 ,  G11C11/56 ,  G11C23/00

    摘要： There are provided a multi-bit electro-mechanical memory device capable of enhancing or maximizing a degree of integration of the memory device and a method of manufacturing the multi-bit electro-mechanical memory device which includes a substrate, a bit line on the substrate, and extending in a first direction; a word line on the bit line, insulated from the bit line, and extending in a second direction transverse to the first direction, and a cantilever electrode including a shape memory alloy. The cantilever electrode has a first portion electrically connected to the bit line and a second portion extending in the first direction, and spaced apart from the word line by an air gap, wherein the cantilever electrode, in a first state, is in electrical contact with the word line, and, in a second state, is spaced apart from the word line.

    摘要翻译： 提供了能够增强或最大化存储器件的集成度的多位机电存储器件和制造多位机电存储器件的方法，该多位机电存储器件包括衬底，衬底上的位线 并且沿第一方向延伸; 位线上的字线，与位线绝缘，并且沿与第一方向横切的第二方向延伸，以及包括形状记忆合金的悬臂电极。 所述悬臂电极具有电连接到所述位线的第一部分和沿所述第一方向延伸的第二部分，并且通过气隙与所述字线间隔开，其中所述悬臂电极在第一状态下与所述第一状态电接触 字线，并且在第二状态下与字线间隔开。

    Memory device and method of fabricating the same
    4.
    发明申请
    Memory device and method of fabricating the same 有权
    存储器件及其制造方法

    公开(公告)号：US20080185668A1

    公开(公告)日：2008-08-07

    申请号：US12007819

    申请日：2008-01-16

    申请人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

    发明人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

    IPC分类号： H01L29/84 ,  H01L21/00

    CPC分类号： G11C11/56 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/16 ,  H01L29/0665 ,  H01L29/0673

    摘要： A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.

    摘要翻译： 存储器件可以包括衬底，位线，至少第一下部字线，至少第一陷阱位置，焊盘电极，至少第一悬臂电极和/或至少第一上部字线。 位线可以在第一方向上形成在基板上。 第一下部字线和第一陷阱位置可以与位线绝缘并且沿与该位线交叉的第二方向形成。 焊盘电极可以在第一下字线和第一陷阱位置的侧壁处绝缘并连接到位线。 第一悬臂电极可以形成在第一方向上，连接到焊盘电极，浮在第一陷阱位置上，具有至少第一下部空的空间，和/或构造成沿第三方向弯曲。 第一上部字线可以在第二方向上的第一悬臂电极上形成有至少第一上部空置空间。

    Multi-bit electro-mechanical memory device and method of manufacturing the same
    5.
    发明申请
    Multi-bit electro-mechanical memory device and method of manufacturing the same 失效
    多位机电记忆体装置及其制造方法

    公开(公告)号：US20080144364A1

    公开(公告)日：2008-06-19

    申请号：US12002668

    申请日：2007-12-18

    申请人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-Jung Yun ,  Dong-Gun Park

    发明人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-Jung Yun ,  Dong-Gun Park

    IPC分类号： G11C11/50 ,  H01L21/00

    CPC分类号： H01L29/788 ,  G11C11/56 ,  G11C23/00

    摘要： There are provided a multi-bit electromechanical memory device capable of enhancing or maximizing a degree of integration of the memory device and a method of manufacturing the multi-bit electromechanical memory device which includes a substrate, a bit line on the substrate, and extending in a first direction; a word line on the bit line, insulated from the bit line, and extending in a second direction transverse to the first direction, and a cantilever electrode including a shape memory alloy. The cantilever electrode has a first portion electrically connected to the bit line and a second portion extending in the first direction, and spaced apart from the word line by an air gap, wherein the cantilever electrode, in a first state, is in electrical contact with the word line, and, in a second state, is spaced apart from the word line.

    摘要翻译： 提供了能够增强或最大化存储器件的集成度的多位机电存储器件以及制造多位机电存储器件的方法，该多位机电存储器件包括衬底，衬底上的位线，并且在 第一个方向 位线上的字线，与位线绝缘，并且沿与第一方向横切的第二方向延伸，以及包括形状记忆合金的悬臂电极。 所述悬臂电极具有电连接到所述位线的第一部分和沿所述第一方向延伸的第二部分，并且通过气隙与所述字线间隔开，其中所述悬臂电极在第一状态下与所述第一状态电接触 字线，并且在第二状态下与字线间隔开。

    Non-volatile memory device and method of fabricating the same
    6.
    发明申请
    Non-volatile memory device and method of fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20080094895A1

    公开(公告)日：2008-04-24

    申请号：US11803425

    申请日：2007-05-15

    申请人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Dong-Gun Park ,  Eun-Jung Yun

    发明人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Dong-Gun Park ,  Eun-Jung Yun

    IPC分类号： G11C11/34 ,  H01L21/44

    CPC分类号： H01L27/101 ,  H01L27/24

    摘要： A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device. In one embodiment, a non-volatile memory device comprises a first word line and a second word line insulated from each other and positioned to intersect each other with a vacant space therebetween; a bit line in the vacant space between one of the first word line and the second word line and positioned in parallel with one of the first word line and the second word line, the bit line constructed and arranged to be deflected toward one of the first word line and the second word line by an electric field induced between the first word line and the second word line; and a trap site between the bit line and one of the first word line and the second word line intersecting the bit line, the trap site being insulated from the one of the first word line and the second word line intersecting the bit line and spaced apart from the bit line by a portion of the vacant space, the trap site configured to trap a predetermined electric charge to electrostatically fix the bit line in a deflected position in the direction of the one of the word lines.

    摘要翻译： 非易失性存储器件及其形成方法增加或最大化超微结构器件的性能。 在一个实施例中，非易失性存储器件包括第一字线和第二字线，该第一字线和第二字线彼此绝缘并且被定位成彼此相交并具有空隙; 位于第一字线和第二字线中的一个之间的空白空间中的位线，并且与第一字线和第二字线之一平行地定位，位线被构造和布置成朝向第一字线 字线和第二字线由在第一字线和第二字线之间感应的电场; 位线与位线相交的第一字线和第二字线之一之间的陷阱位置，陷阱位置与第一字线和第二字线之一绝缘，与位线相交并间隔开 从位线通过空闲空间的一部分，陷阱位置被配置为捕获预定电荷以将位线静电地固定在一条字线的方向上的偏转位置。

    Metal oxide semiconductor (MOS) transistors having three dimensional channels
    10.
    发明授权
    Metal oxide semiconductor (MOS) transistors having three dimensional channels 有权
    具有三维通道的金属氧化物半导体（MOS）晶体管

    公开(公告)号：US07473963B2

    公开(公告)日：2009-01-06

    申请号：US11854734

    申请日：2007-09-13

    申请人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    发明人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7842

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.

    摘要翻译： 金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。 第一和第二沟道区设置在源区和漏区之间。 沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。 第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。 在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。