公开(公告)号：US08018764B2

公开(公告)日：2011-09-13

申请号：US12461062

申请日：2009-07-30

申请人： Sung-chul Lee ,  Jai-kwang Shin ,  Sun-ae Seo ,  Young-jin Cho ,  Ung-hwan Pl ,  Ji-young Bae

发明人： Sung-chul Lee ,  Jai-kwang Shin ,  Sun-ae Seo ,  Young-jin Cho ,  Ung-hwan Pl ,  Ji-young Bae

IPC分类号： G11C11/14

CPC分类号： G11C19/0808 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic track includes first and second magnetic domain regions having different lengths and different magnetic domain wall movement speeds. A longer of the first and second magnetic domain regions serves as an information read/write region. An information storage device includes a magnetic track. The magnetic track includes a plurality of magnetic domain regions and a magnetic domain wall region formed between neighboring magnetic domain regions. The plurality of magnetic domain regions includes a first magnetic domain region and at least one second magnetic domain region having a smaller length than the first magnetic domain region. The information storage device further includes a first unit configured to perform at least one of an information recording operation and an information reproducing operation on the first magnetic domain region, and a magnetic domain wall movement unit configured to move a magnetic domain wall of the magnetic domain wall region.

摘要翻译： 磁道包括具有不同长度和不同磁畴壁移动速度的第一和第二磁畴区域。 第一和第二磁畴区域中较长的区域用作信息读/写区域。 信息存储装置包括磁道。 磁道包括多个磁畴区域和形成在相邻磁畴区域之间的磁畴壁区域。 多个磁畴区域包括第一磁畴区域和具有比第一磁畴区域更小的长度的至少一个第二磁畴区域。 信息存储装置还包括被配置为在第一磁畴区域上执行信息记录操作和信息再现操作中的至少一个的第一单元和被配置为移动磁畴的磁畴壁的磁畴壁移动单元 墙区域。

公开(公告)号：US20100149863A1

公开(公告)日：2010-06-17

申请号：US12461062

申请日：2009-07-30

申请人： Sung-chul Lee ,  Jai-kwang Shin ,  Sun-ae Seo ,  Young-jin Cho ,  Ung-hwan Pl ,  Ji-young Bae

发明人： Sung-chul Lee ,  Jai-kwang Shin ,  Sun-ae Seo ,  Young-jin Cho ,  Ung-hwan Pl ,  Ji-young Bae

IPC分类号： G11C11/14

CPC分类号： G11C19/0808 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic track includes first and second magnetic domain regions having different lengths and different magnetic domain wall movement speeds. A longer of the first and second magnetic domain regions serves as an information read/write region. An information storage device includes a magnetic track. The magnetic track includes a plurality of magnetic domain regions and a magnetic domain wall region formed between neighboring magnetic domain regions. The plurality of magnetic domain regions includes a first magnetic domain region and at least one second magnetic domain region having a smaller length than the first magnetic domain region. The information storage device further includes a first unit configured to perform at least one of an information recording operation and an information reproducing operation on the first magnetic domain region, and a magnetic domain wall movement unit configured to move a magnetic domain wall of the magnetic domain wall region.

摘要翻译： 磁道包括具有不同长度和不同磁畴壁移动速度的第一和第二磁畴区域。 第一和第二磁畴区域中较长的区域用作信息读/写区域。 信息存储装置包括磁道。 磁道包括多个磁畴区域和形成在相邻磁畴区域之间的磁畴壁区域。 多个磁畴区域包括第一磁畴区域和具有比第一磁畴区域更小的长度的至少一个第二磁畴区域。 信息存储装置还包括被配置为在第一磁畴区域上执行信息记录操作和信息再现操作中的至少一个的第一单元和被配置为移动磁畴的磁畴壁的磁畴壁移动单元 墙区域。

公开(公告)号：US08089797B2

公开(公告)日：2012-01-03

申请号：US12659515

申请日：2010-03-11

申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Sun-ae Seo ,  Sung-chul Lee

发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Sun-ae Seo ,  Sung-chul Lee

IPC分类号： G11C19/00

CPC分类号： G11C19/0808 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A memory cell includes: a memory cell array unit having a plurality of nano wires arranged vertically on a substrate, each of the plurality of nano wires having a plurality of domains for storing information; a nano wire selection unit formed on the substrate and configured to select at least one of the plurality of nano wires; a domain movement control unit formed on the substrate and configured to control a domain movement operation with respect to at least one of the plurality of nano wires; and a read/write control unit formed on the substrate and configured to control at least one of a read operation and a write operation with respect to at least one of the plurality of nano wires.

摘要翻译： 存储单元包括：存储单元阵列单元，具有垂直地布置在基板上的多个纳米线，所述多个纳米线中的每一个具有用于存储信息的多个域; 形成在所述基板上并被配置为选择所述多个纳米线中的至少一个的纳米线选择单元; 域移动控制单元，形成在所述基板上，并且被配置为控制相对于所述多个纳米线中的至少一个的域移动操作; 以及读/写控制单元，形成在所述基板上并被配置为控制关于所述多根纳米线中的至少一个的读取操作和写入操作中的至少一个。

公开(公告)号：US20110063885A1

公开(公告)日：2011-03-17

申请号：US12659515

申请日：2010-03-11

申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Sun-ae Seo ,  Sung-chul Lee

发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Sun-ae Seo ,  Sung-chul Lee

IPC分类号： G11C19/00 ,  G11C7/00

CPC分类号： G11C19/0808 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A memory cell includes: a memory cell array unit having a plurality of nano wires arranged vertically on a substrate, each of the plurality of nano wires having a plurality of domains for storing information; a nano wire selection unit formed on the substrate and configured to select at least one of the plurality of nano wires; a domain movement control unit formed on the substrate and configured to control a domain movement operation with respect to at least one of the plurality of nano wires; and a read/write control unit formed on the substrate and configured to control at least one of a read operation and a write operation with respect to at least one of the plurality of nano wires.

摘要翻译： 存储单元包括：存储单元阵列单元，具有垂直地布置在基板上的多个纳米线，所述多个纳米线中的每一个具有用于存储信息的多个域; 形成在所述基板上并被配置为选择所述多个纳米线中的至少一个的纳米线选择单元; 域移动控制单元，形成在所述基板上，并且被配置为控制相对于所述多个纳米线中的至少一个的域移动操作; 以及读/写控制单元，形成在所述基板上并被配置为控制关于所述多根纳米线中的至少一个的读取操作和写入操作中的至少一个。

公开(公告)号：US08310014B2

公开(公告)日：2012-11-13

申请号：US13317734

申请日：2011-10-27

申请人： David Seo ,  Jai-kwang Shin ,  Sun-ae Seo

发明人： David Seo ,  Jai-kwang Shin ,  Sun-ae Seo

IPC分类号： H01L29/78

CPC分类号： H01L21/3146 ,  H01L21/02115 ,  H01L21/02269 ,  H01L21/0237 ,  H01L21/02444 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02631 ,  H01L29/1606 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78681 ,  H01L29/78684

摘要： Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10−11 Torr or less prior to performing an epitaxy process, and supplying a carbon source to the chamber to form a carbon insulating layer on the substrate. The carbon insulating layer is formed of diamond-like carbon and tetrahedral amorphous carbon.

公开(公告)号：US08084371B2

公开(公告)日：2011-12-27

申请号：US12923240

申请日：2010-09-10

申请人： David Seo ,  Jai-kwang Shin ,  Sun-ae Seo

发明人： David Seo ,  Jai-kwang Shin ,  Sun-ae Seo

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/8236

CPC分类号： H01L21/3146 ,  H01L21/02115 ,  H01L21/02269 ,  H01L21/0237 ,  H01L21/02444 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02631 ,  H01L29/1606 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78681 ,  H01L29/78684

摘要： Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10−11 Torr or less prior to performing an epitaxy process, and supplying a carbon source to the chamber to form a carbon insulating layer on the substrate. The carbon insulating layer is formed of diamond-like carbon and tetrahedral amorphous carbon.

摘要翻译： 提供场效应晶体管，使用分子束外延制造碳绝缘层的方法和使用其制造场效应晶体管的方法，制造碳绝缘层的方法包括将设置在分子束外延室中的衬底保持在 温度在约300℃至约500℃的范围内，并且在进行外延过程之前将室维持在10-11乇或更小的真空度，并将碳源供应到室以形成碳绝缘层 在基板上。 碳绝缘层由菱形碳和四面体无定形碳形成。

公开(公告)号：US20120043625A1

公开(公告)日：2012-02-23

申请号：US13317734

申请日：2011-10-27

申请人： David Seo ,  Jai-kwang Shin ,  Sun-ae Seo

发明人： David Seo ,  Jai-kwang Shin ,  Sun-ae Seo

IPC分类号： H01L29/78

CPC分类号： H01L21/3146 ,  H01L21/02115 ,  H01L21/02269 ,  H01L21/0237 ,  H01L21/02444 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02631 ,  H01L29/1606 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78681 ,  H01L29/78684

摘要： Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10−11 Torr or less prior to performing an epitaxy process, and supplying a carbon source to the chamber to form a carbon insulating layer on the substrate. The carbon insulating layer is formed of diamond-like carbon and tetrahedral amorphous carbon.

摘要翻译： 提供场效应晶体管，使用分子束外延制造碳绝缘层的方法和使用其制造场效应晶体管的方法，制造碳绝缘层的方法包括将设置在分子束外延室中的衬底保持在 温度在约300℃至约500℃的范围内，并且在进行外延过程之前将室维持在10-11乇或更小的真空度，并将碳源供应到室以形成碳绝缘层 在基板上。 碳绝缘层由菱形碳和四面体无定形碳形成。

公开(公告)号：US07978006B2

公开(公告)日：2011-07-12

申请号：US12585724

申请日：2009-09-23

申请人： Jai-kwang Shin ,  Sun-ae Seo ,  Jong-seob Kim ,  Ki-ha Hong ,  Hyun-jong Chung

发明人： Jai-kwang Shin ,  Sun-ae Seo ,  Jong-seob Kim ,  Ki-ha Hong ,  Hyun-jong Chung

IPC分类号： H01L25/00

CPC分类号： H01L29/7613 ,  B82Y10/00 ,  H01L29/1029 ,  H01L29/16 ,  H01L29/1606 ,  H01L29/66977

摘要： A quantum interference transistor may include a source; a drain; N channels (N≧2), between the source and the drain, and having N−1 path differences between the source and the drain; and at least one gate disposed at one or more of the N channels. One or more of the N channels may be formed in a graphene sheet. A method of manufacturing the quantum interference transistor may include forming one or more of the N channels using a graphene sheet. A method of operating the quantum interference transistor may include applying a voltage to the at least one gate. The voltage may shift a phase of a wave of electrons passing through a channel at which the at least one gate is disposed.

摘要翻译： 量子干涉晶体管可以包括源极; 排水 在源极和漏极之间的N沟道（N≥2），源极和漏极之间具有N-1个路径差; 以及设置在所述N个通道中的一个或多个的至少一个门。 N个通道中的一个或多个可以形成在石墨烯片中。 制造量子干涉晶体管的方法可以包括使用石墨烯片形成N个通道中的一个或多个。 操作量子干涉晶体管的方法可以包括向至少一个栅极施加电压。 电压可以使通过通道的电子的波的相位偏移至设置至少一个栅极的通道。

公开(公告)号：US20110121409A1

公开(公告)日：2011-05-26

申请号：US12923240

申请日：2010-09-10

申请人： David Seo ,  Jai-kwang Shin ,  Sun-ae Seo

发明人： David Seo ,  Jai-kwang Shin ,  Sun-ae Seo

IPC分类号： H01L29/78 ,  H01L21/314 ,  H01L21/336

CPC分类号： H01L21/3146 ,  H01L21/02115 ,  H01L21/02269 ,  H01L21/0237 ,  H01L21/02444 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02631 ,  H01L29/1606 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78681 ,  H01L29/78684

摘要： Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10−11 Torr or less prior to performing an epitaxy process, and supplying a carbon source to the chamber to form a carbon insulating layer on the substrate. The carbon insulating layer is formed of diamond-like carbon and tetrahedral amorphous carbon.

公开(公告)号：US20100090759A1

公开(公告)日：2010-04-15

申请号：US12585724

申请日：2009-09-23

申请人： Jai-kwang Shin ,  Sun-ae Seo ,  Jong-seob Kim ,  Ki-ha Hong ,  Hyun-jong Chung

发明人： Jai-kwang Shin ,  Sun-ae Seo ,  Jong-seob Kim ,  Ki-ha Hong ,  Hyun-jong Chung

IPC分类号： H03H11/24 ,  H01L29/66 ,  H01L21/336

CPC分类号： H01L29/7613 ,  B82Y10/00 ,  H01L29/1029 ,  H01L29/16 ,  H01L29/1606 ,  H01L29/66977

摘要： A quantum interference transistor may include a source; a drain; N channels (N≧2), between the source and the drain, and having N−1 path differences between the source and the drain; and at least one gate disposed at one or more of the N channels. One or more of the N channels may be formed in a graphene sheet. A method of manufacturing the quantum interference transistor may include forming one or more of the N channels using a graphene sheet. A method of operating the quantum interference transistor may include applying a voltage to the at least one gate. The voltage may shift a phase of a wave of electrons passing through a channel at which the at least one gate is disposed.

摘要翻译： 量子干涉晶体管可以包括源极; 排水 在源极和漏极之间的N沟道（N≥2），源极和漏极之间具有N-1个路径差; 以及设置在所述N个通道中的一个或多个的至少一个门。 N个通道中的一个或多个可以形成在石墨烯片中。 制造量子干涉晶体管的方法可以包括使用石墨烯片形成N个通道中的一个或多个。 操作量子干涉晶体管的方法可以包括向至少一个栅极施加电压。 电压可以使通过通道的电子的波的相位偏移至设置至少一个栅极的通道。