公开(公告)号：US6134622A

公开(公告)日：2000-10-17

申请号：US13777

申请日：1998-01-26

申请人： Suvansh Kapur ,  Kevin Koschoreck ,  Srinand Venkatesan ,  D. Michael Bell

发明人： Suvansh Kapur ,  Kevin Koschoreck ,  Srinand Venkatesan ,  D. Michael Bell

IPC分类号： G06F9/38 ,  G06F13/40 ,  G06F13/38

CPC分类号： G06F9/3824 ,  G06F13/4045 ,  G06F13/4059 ,  G06F13/4081

摘要： A bus expander bridge is provided for interfacing first and second external buses (such as PCI buses) to a third bus. The bus expander bridge is configurable in either an independent mode in which the first and second external buses operate independently and a combined mode in which the first and second external buses are combined to create a single bus. The bus expander bridge includes a first set of data queues for routing data between the first external bus and the third bus, and a second set of data queues for routing data between the second external bus and the third bus. The bus expander bridge also includes a controller coupled to the first and second sets of data queues and operating the first and second sets of data queues in parallel for the independent mode. The controller routes even addressed data through the first set of data queues and routes odd addressed data through the second set of data queues for the combined mode.

摘要翻译： 提供一个总线扩展器桥接器用于将第一和第二外部总线（例如PCI总线）与第三总线接口。 总线扩展器桥可以以独立模式配置，其中第一和第二外部总线独立运行，以及组合模式，其中组合第一和第二外部总线以创建单个总线。 总线扩展器桥包括用于在第一外部总线和第三总线之间路由数据的第一组数据队列，以及用于在第二外部总线和第三总线之间路由数据的第二组数据队列。 总线扩展器桥还包括耦合到第一和第二组数据队列的控制器，并且为独立模式并行地操作第一和第二组数据队列。 控制器通过第一组数据队列路由寻址数据，并通过组合模式的第二组数据队列路由奇数寻址数据。

公开(公告)号：US5535340A

公开(公告)日：1996-07-09

申请号：US247026

申请日：1994-05-20

申请人： D. Michael Bell ,  Mark A. Gonzales ,  Susan S. Meredith

发明人： D. Michael Bell ,  Mark A. Gonzales ,  Susan S. Meredith

IPC分类号： G06F13/36 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4027

摘要： A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Decoding circuitry within the bridge issues a deferred response if the request can be deferred. This deferred response is returned to the originating agent on the first bus, thereby informing the originating agent that the request will be serviced at a later time. Bus control circuitry coupled to the outbound request queue removes requests from the outbound request queue and executes them on the second bus. The bus control circuitry receives a response from the destination agent on the second bus in response to the execution of the outbound request. This response is returned to the originating agent either immediately or after passing through an inbound request queue. Both the outbound request queue and the inbound request queue have data buffers associated therewith for transferring data between the two buses. In addition, requests may originate on the second bus which target a device on the first bus (i.e., inbound requests). These inbound requests are placed in the inbound request queue and are executed on the first bus when removed from the inbound request queue.

摘要翻译： 位于两条总线之间的总线桥包括两个队列：出站请求队列和入站请求队列。 在第二个总线上的目的地的第一个总线上产生的请求被放置在出站请求队列中。 如果请求可以推迟，桥内的解码电路会发出延迟响应。 该延迟响应在第一总线上返回给始发代理，从而通知始发代理该请求将在稍后的时间被服务。 耦合到出站请求队列的总线控制电路从出站请求队列中移除请求，并在第二个总线上执行它们。 总线控制电路响应于执行出站请求而从第二总线上的目的地代理接收响应。 此响应将立即或通过入站请求队列后返回给始发代理。 出站请求队列和入站请求队列都有与之相关联的数据缓冲区，用于在两条总线之间传输数据。 此外，请求可以来自在第一总线上的设备（即，入站请求）上的第二总线上。 这些入站请求被放置在入站请求队列中，并在从入站请求队列中删除时在第一个总线上执行。

公开(公告)号：US6070207A

公开(公告)日：2000-05-30

申请号：US137164

申请日：1998-08-20

申请人： D. Michael Bell

发明人： D. Michael Bell

IPC分类号： G06F13/40 ,  G06F13/00 ,  G06F1/24

CPC分类号： G06F13/4081

摘要： A computer system includes a host processor coupled to a host bus. The computer system also includes a memory system coupled to the host bus, and an I/O bridge controller coupled to the host bus and including a plurality of ports. An I/O bus bridge is provided that is hot plug connectable to at least one of the bridge controller ports via one or more first buses. There are one or more second buses coupled to the I/O bus bridge.

摘要翻译： 计算机系统包括耦合到主机总线的主机处理器。 计算机系统还包括耦合到主机总线的存储器系统和耦合到主机总线并包括多个端口的I / O桥接器控制器。 提供了一种I / O总线桥，其是通过一个或多个第一总线可连接到至少一个桥控制器端口的热插头。 耦合到I / O总线桥的一个或多个第二总线。

公开(公告)号：US5905876A

公开(公告)日：1999-05-18

申请号：US766954

申请日：1996-12-16

申请人： Stephen S. Pawlowski ,  Peter D. MacWilliams ,  D. Michael Bell

发明人： Stephen S. Pawlowski ,  Peter D. MacWilliams ,  D. Michael Bell

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/14

CPC分类号： G06F13/1642 ,  G06F12/0835

摘要： A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the computing system, and facilitates concurrence of the transactions so as to enable high-bandwidth, deadlock-free operation. I/O to memory transactions and processor to memory transactions are placed in a memory request queue in the order in which such transactions appear on the processor bus; I/O to memory transactions are placed in an inbound request queue in the order such transactions appear on the I/O bus; and processor to I/O transactions and completions corresponding to split-transaction I/O to memory read transactions are placed in an outbound request queue in the order in which the split-transaction I/O to memory read transactions and the processor to I/O transactions appear on the processor bus.

摘要翻译： 用于基于处理器的计算系统的事务排序机制确保处理器，I / O和存储器子系统之间的事务的正确排序，确保计算系统内的高速缓存一致性，并且有助于并发交易，从而实现高带宽， 免费操作。 存储器事务的I / O和处理器到存储器事务按照这种事务在处理器总线上出现的顺序被放置在存储器请求队列中; 存储器事务的I / O按照这种事务出现在I / O总线上的顺序放置在入站请求队列中; 并且处理器到I / O事务和对应于分割事务I / O到存储器读取事务的完成被放置在出站请求队列中，其中分割事务I / O到存储器读取事务和处理器到I / O事务出现在处理器总线上。

公开(公告)号：US5828865A

公开(公告)日：1998-10-27

申请号：US579297

申请日：1995-12-27

申请人： D. Michael Bell

发明人： D. Michael Bell

IPC分类号： G06F9/38 ,  G06F13/40 ,  G06F9/318

CPC分类号： G06F9/3824 ,  G06F13/4045 ,  G06F13/4059 ,  G06F13/4081

摘要： The dual mode bus bridge accommodates either two 64-bit personal computer interface (PCI) buses or four 32-bit PCI buses. In either case, only a single load is applied to the host bus. The dual mode bridge includes a bridge controller unit connected to a pair of expansion bridge units by respective internal buses. Each expansion bridge unit includes two sets of 64-bit wide queues and buffers. For 32-bit PCI operation, the two sets of queues and buffers are operated in parallel. For 64-bit PCI operation, the two sets of queues and buffers are linked together so as to appear in series to provide a single queue structure having twice the depth of the separate queue structures for a 32-bit mode operation. As such, undue duplication of queue and buffer resources is avoided. Method and apparatus embodiments of the invention are described.

公开(公告)号：US5410707A

公开(公告)日：1995-04-25

申请号：US204820

申请日：1994-03-01

申请人： D. Michael Bell

发明人： D. Michael Bell

IPC分类号： G06F1/00 ,  G06F1/24 ,  G06F3/023 ,  G06F9/445

CPC分类号： G06F9/4403 ,  G06F1/24 ,  G06F3/023

摘要： A computer system bootstrap loads a processor and associated memory from an external memory device instead of being bootstrap loaded from on-board read only memory. The computer system is comprised of a system bus, a processing component, a first system memory device, a memory card interface controller, and an external memory device connected to the memory card interface controller. The system also includes a second system memory device, a keyboard memory device, a keyboard controller and a reset switch for causing a reset and initialization of the processing component. Upon reset, the logic in the memory card interface controller remaps the address space associated with the first system memory device to the external memory device and remaps the address space associated with the second system memory device to the keyboard memory device. This remapping redirects execution control of the processing component to the external memory device and allows the keyboard memory device to be loaded and verified by the processing component. The keyboard controller is held in a reset state. Once the keyboard memory device and local random access memory has been loaded from the external memory device, the address space remapping of the first and second memory devices is restored to a normal configuration. The contents of the first and second memory devices can then be loaded and verified. The reset condition is then removed from the keyboard controller and normal operation of the computer system is restored.

摘要翻译： 计算机系统引导程序从外部存储设备加载处理器和关联的存储器，而不是从板上只读存储器加载引导。 计算机系统由系统总线，处理部件，第一系统存储器件，存储卡接口控制器和连接到存储卡接口控制器的外部存储器件组成。 该系统还包括第二系统存储设备，键盘存储设备，键盘控制器和用于引起处理组件的复位和初始化的复位开关。 在复位时，存储卡接口控制器中的逻辑将与第一系统存储器设备相关联的地址空间重新映射到外部存储器设备，并将与第二系统存储器设备相关联的地址空间重新映射到键盘存储设备。 该重新映射将处理组件的执行控制重定向到外部存储器设备，并且允许由处理组件加载和验证键盘存储器设备。 键盘控制器保持在复位状态。 一旦从外部存储器装置加载了键盘存储装置和本地随机存取存储器，则将第一和第二存储装置的地址空间重映射恢复到正常配置。 然后可以加载和验证第一和第二存储器件的内容。 然后从键盘控制器中移除复位条件，恢复计算机系统的正常操作。

公开(公告)号：US07480747B2

公开(公告)日：2009-01-20

申请号：US11147991

申请日：2005-06-08

申请人： D. Michael Bell ,  Anil Vasudevan

发明人： D. Michael Bell ,  Anil Vasudevan

IPC分类号： G06F13/00

CPC分类号： G06F13/4022

摘要： Some embodiments include apparatus and method having a register circuit to receive a first portion of a packet from an input/output device, cache memory circuit to receive a second portion of the package, and a processing unit to process at least one of the first and second portions of the packet based on instructions in the processing unit. The processing unit and the register circuit reside on a processor. The first portion of the packet is placed into the register circuit of the processor, bypassing a memory device coupled to the processor. The second portion of the packet is placed into the cache memory circuit of the processor, bypassing the memory device.

摘要翻译： 一些实施例包括具有用于从输入/输出设备接收分组的第一部分的寄存器电路的设备和方法，用于接收该包的第二部分的高速缓存存储器电路，以及处理单元，用于处理第一和第 基于处理单元中的指令，分组的第二部分。 处理单元和寄存器电路驻留在处理器上。 分组的第一部分被放置在处理器的寄存器电路中，绕过与处理器耦合的存储器件。 分组的第二部分被放置在处理器的高速缓冲存储器电路中，绕过存储器件。

公开(公告)号：US07107371B1

公开(公告)日：2006-09-12

申请号：US08934968

申请日：1997-09-22

申请人： D. Michael Bell

发明人： D. Michael Bell

IPC分类号： G06F1/00

CPC分类号： G06F13/4226

摘要： A system and method for sending device specific data in a bus transaction. A device configurable field is preallocated in a packet sent by the sending device to a receiving device. The sending device can configure the data to be stored in the device configurable field. Upon receipt of the packet, the receiving device generates a response packet in which the contents of the device configurable field is simply copied into a corresponding field in the response packet.

摘要翻译： 一种用于在总线事务中发送设备特定数据的系统和方法。 设备可配置字段在由发送设备发送到接收设备的分组中预先分配。 发送设备可以配置存储在设备可配置字段中的数据。 在接收到该分组时，接收设备生成响应分组，其中设备可配置字段的内容被简单地复制到响应分组中的相应字段中。

公开(公告)号：US06108736A

公开(公告)日：2000-08-22

申请号：US934996

申请日：1997-09-22

申请人： D. Michael Bell

发明人： D. Michael Bell

IPC分类号： G06F13/14 ,  G06F13/00

CPC分类号： G06F13/14

摘要： A system and method for controlling the flow of information between devices. A count is maintained representative of requests issued by a first device. The count is incremented for each packet issued by a first device and decremented for each packet received at the first device. A maximum buffer count, which corresponds to the capacity of the buffer is used to perform flow control by determining when the maximum buffer count is to be exceeded by the issuance of a packet by the first device. If the count is to be exceed, issuance of packets by the first device is prevented until the maximum buffer count will not be exceeded by issuance of the packet.

摘要翻译： 一种用于控制设备之间的信息流的系统和方法。 保持代表由第一设备发出的请求的计数。 对于由第一设备发布的每个分组，计数递增，并且对于在第一设备处接收到的每个分组递减计数。 对应于缓冲器的容量的最大缓冲器计数用于通过由第一设备发布数据包来确定何时超过最大缓冲器计数来执行流量控制。 如果计数超过，则防止第一设备发送数据包，直到发送数据包不会超过最大缓冲区数。

公开(公告)号：US5835739A

公开(公告)日：1998-11-10

申请号：US889756

申请日：1997-07-10

申请人： D. Michael Bell ,  Mark A. Gonzales ,  Susan S. Meredith

发明人： D. Michael Bell ,  Mark A. Gonzales ,  Susan S. Meredith

IPC分类号： G06F13/00 ,  G06F13/362 ,  G06F13/40

CPC分类号： G06F13/4004 ,  G06F13/362 ,  G06F13/4027 ,  G06F13/4031 ,  G06F13/4036

摘要： A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus. The TAU determines whether posting to the inbound request queue is enabled or disabled; whether any posted transactions exist in the inbound request queue; and whether ownership of the second bus is available.