公开(公告)号：US06301631B1

公开(公告)日：2001-10-09

申请号：US09239500

申请日：1999-01-28

Applicant: Peter Chambers ,  Subramanian S. Meiyappan ,  Swaroop Adusumilli

Inventor： Peter Chambers ,  Subramanian S. Meiyappan ,  Swaroop Adusumilli

IPC: G06F1314

CPC classification number: G06F13/16

Abstract: A system and method that prevents address aliasing and eliminates the unnecessary clock cycle consumed by the use of a dual address cycle when using a single address cycle to transmit a target address in a computer system including target devices having addresses of different sizes, such as 32-bit and 64-bit target devices, with 32-bit and 64-bit addresses, respectively. In addition, a combination of single address cycles and dual address cycles may be used to prevent address aliasing while permitting access to the entire address spaces of the target devices. The computer system includes a bus, an initiator device coupled to the bus, a first target device coupled to the bus, and a second target device coupled to the bus. The first target device has a first address range containing a plurality of bits, and the second target device has a second address range containing a fewer number of bits than the first address range. The second address range includes addresses that are specified according to a first prescribed value for a most significant bit. The first address range includes addresses that are specified according to a second prescribed value for the most significant bit to exclude the second address range such that the initiator device can transmit the first address to the first target device without aliasing the second address with the first address. The initiator device selects either the first address range or the second address range for the target address by specifying either the first prescribed value or the second prescribed value in the target address.

Abstract translation: 一种防止地址混叠的系统和方法，并且消除了当使用单个地址周期在包括具有不同大小的地址的目标设备的计算机系统中传送目标地址时使用双地址周期而消耗的不必要的时钟周期，诸如32 位和64位目标器件，分别具有32位和64位地址。 此外，可以使用单个地址周期和双地址周期的组合来防止地址别名，同时允许访问目标设备的整个地址空间。 计算机系统包括总线，耦合到总线的启动器设备，耦合到总线的第一目标设备以及耦合到总线的第二目标设备。 第一目标设备具有包含多个比特的第一地址范围，并且第二目标设备具有包含比第一地址范围少的比特数的第二地址范围。 第二地址范围包括根据最高有效位的第一规定值指定的地址。 第一地址范围包括根据用于排除第二地址范围的最高有效位的第二规定值指定的地址，使得发起者设备可以将第一地址发送到第一目标设备，而不将第一地址与第一地址进行混叠 。 启动器设备通过指定目标地址中的第一规定值或第二规定值来选择目标地址的第一地址范围或第二地址范围。

公开(公告)号：US06178478B1

公开(公告)日：2001-01-23

申请号：US09210103

申请日：1998-12-11

Applicant: Peter Chambers ,  Subramanian S. Meiyappan ,  Swaroop Adusumilli

Inventor： Peter Chambers ,  Subramanian S. Meiyappan ,  Swaroop Adusumilli

IPC: G06F1300

CPC classification number: G06F13/4004 ,  G06F13/423

Abstract: A system and method for preventing address aliasing when using a single address cycle to transmit a target address in a computer system that includes target devices having addresses of different ranges. The computer system comprises a bus, an initiator device coupled to the bus, a first target device coupled to the bus, and a second target device coupled to the bus. The first target device has a first address range comprising a plurality of bits, and the second target device has a second address range comprising a fewer number of bits than the first address range. The initiator device transmits a signal indicating the size of the target address and also separately transmits in a single address cycle the target address. The second target device disables its address decode logic in response to the signal from the initiator device provided that the size of the target address is greater than the second address range. The second target device is thus prevented from responding to the target address, thereby preventing address aliasing.

Abstract translation: 一种用于在使用单个地址周期在包括具有不同范围的地址的目标设备的计算机系统中发送目标地址时防止地址混叠的系统和方法。 计算机系统包括总线，耦合到总线的启动器设备，耦合到总线的第一目标设备和耦合到总线的第二目标设备。 第一目标设备具有包括多个比特的第一地址范围，并且第二目标设备具有包括比第一地址范围少的比特数的第二地址范围。 发起者设备发送指示目标地址的大小的信号，并且在单个地址周期中分别发送目标地址。 如果目标地址的大小大于第二地址范围，则第二目标设备响应于来自发起者设备的信号而禁用其地址解码逻辑。 从而防止第二目标设备响应目标地址，从而防止地址混叠。

公开(公告)号：US06289406B1

公开(公告)日：2001-09-11

申请号：US09187325

申请日：1998-11-06

Applicant: Peter Chambers ,  Swaroop Adusumilli ,  Subramanian S. Meiyappan

Inventor： Peter Chambers ,  Swaroop Adusumilli ,  Subramanian S. Meiyappan

IPC: G06F1314

CPC classification number: G06F13/4027

Abstract: A system and method for completing a read transaction between an initiator device and a host memory device in a computer system, in which the present invention optimizes the retry behavior of the initiator device and a target device. The system of the present invention includes a bus bridge device, wherein the bus bridge device includes a target device coupled to the initiator device via a bus; the host memory device coupled to the bus bridge device; and a timer mechanism coupled to the target device. The initiator device is adapted to initiate a present read transaction via the target device, such that an access is asserted between the initiator device and the target device. The timer mechanism is adapted to measure target latency for one or more read transactions preceding the present read transaction, and the timer mechanism is further adapted to use the target latency to calculate a dynamic target latency period. The target device is adapted to maintain the access to the initiator device during the dynamic target latency period. Thus, in accordance with the present invention, the target latency is dynamically measured and used to optimize the retry behavior of the initiator and target devices.

Abstract translation: 一种用于完成计算机系统中的发起者设备和主机存储设备之间的读取事务的系统和方法，其中本发明优化了发起者设备和目标设备的重试行为。 本发明的系统包括总线桥装置，其中总线桥装置包括经由总线耦合到启动器装置的目标装置; 主机存储设备耦合到总线桥接器件; 以及耦合到目标设备的定时器机构。 启动器设备适于经由目标设备发起当前读取事务，使得在发起者设备和目标设备之间确认访问。 定时器机构适于测量当前读取事务之前的一个或多个读取事务的目标延迟，并且定时器机制还适于使用目标等待时间来计算动态目标等待时间周期。 目标设备适于在动态目标潜伏期期间维持对发起者设备的访问。 因此，根据本发明，动态测量目标延迟并用于优化发起者和目标设备的重试行为。

公开(公告)号：US06230216B1

公开(公告)日：2001-05-08

申请号：US09239461

申请日：1999-01-28

Applicant: Peter Chambers ,  Subramanian S. Meiyappan ,  Swaroop Adusumilli

Inventor： Peter Chambers ,  Subramanian S. Meiyappan ,  Swaroop Adusumilli

IPC: G06F300

CPC classification number: G06F9/30043 ,  G06F9/3875 ,  G06F12/06 ,  G06F13/423

Abstract: A system and method for using single address cycles and eliminating dual address cycles to transmit a target address in a computer system. The computer system comprises a bus, a central processing unit coupled to the bus, an initiator device coupled to the bus, and a target device coupled to the bus. The target device comprises a first configuration register which is adapted to use a configuration bit to indicate an address range of the target device. The central processing unit interrogates the first configuration register and communicates the address range indicated by the configuration bit to the initiator device. The initiator device comprises a second configuration register which is adapted to use a configuration bit to register the address range of the target device. The initiator device is adapted to disable its dual address cycle capability and transmit to the target device the target address in a single address cycle provided that the address range of the target device as indicated by the respective configuration bits in the first and second configuration registers is not less than a size of the target address.

Abstract translation: 一种用于使用单个地址周期并消除双地址周期以在计算机系统中传送目标地址的系统和方法。 计算机系统包括总线，耦合到总线的中央处理单元，耦合到总线的启动器设备以及耦合到总线的目标设备。 目标设备包括第一配置寄存器，其适于使用配置位来指示目标设备的地址范围。 中央处理单元询问第一配置寄存器，并将配置位指示的地址范围传送给启动器设备。 启动器设备包括第二配置寄存器，其适于使用配置位来注册目标设备的地址范围。 启动器设备适于禁用其双地址周期能力并且以单个地址周期向目标设备发送目标地址，只要如第一和第二配置寄存器中的相应配置位所指示的目标设备的地址范围是 不小于目标地址的大小。

公开(公告)号：US06223232B1

公开(公告)日：2001-04-24

申请号：US09255407

申请日：1999-02-22

Applicant: Swaroop Adusumilli ,  Subramanian S. Meiyappan

Inventor： Swaroop Adusumilli ,  Subramanian S. Meiyappan

IPC: G06F1314

CPC classification number: G06F13/4068 ,  G06F13/36 ,  Y02D10/14 ,  Y02D10/151

Abstract: A target configuration prediction system that provides an initiator coupled to a bus system with a prediction of the configuration type of a target. The present invention stores information regarding the address and configuration of targets and utilizes this information to predict the address of a target an initiator is currently attempting to access. The prediction is based upon the proximity of stored target addresses to a target address an initiator is currently trying to access and the probability that targets with addresses within certain ranges are the same target configuration type. The configuration type is determined by initiator component logic during an initial attempt at accessing a target and a status bit indicating the configuration type is stored in a status bit component. In a retry situation, an initiator relies on the status bit indications stored in the status bit component to identify a target configuration, so that the initiator does not engage in configuration determination handshaking with a target in a retry situation.

Abstract translation: 一种目标配置预测系统，其通过对目标的配置类型的预测来提供耦合到总线系统的启动器。 本发明存储关于目标的地址和配置的信息，并利用该信息来预测发起者正在尝试访问的目标的地址。 该预测基于存储的目标地址与发起方当前尝试访问的目标地址的接近度，并且具有特定范围内的地址的目标的概率是相同的目标配置类型。 在初始尝试访问目标期间由配置类型由启动器组件逻辑确定，并且将指示配置类型的状态位存储在状态位组件中。 在重试情况下，启动器依赖于存储在状态位组件中的状态位指示来识别目标配置，使得启动器在重试情况下不与目标进行配置确定握手。

公开(公告)号：US06334198B1

公开(公告)日：2001-12-25

申请号：US09283171

申请日：1999-04-01

Applicant: Swaroop Adusumilli ,  James Steele ,  David Cassetti

Inventor： Swaroop Adusumilli ,  James Steele ,  David Cassetti

IPC: G01R3128

CPC classification number: G01R31/318558 ,  G01R31/318563

Abstract: An arrangement controls an IC designed with multiple “core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled at a time. For applications typically requiring that control be transferred between such TAP controllers, one embodiment of the present invention configures a TLM-based design such that multiple TAP controllers can be simultaneously enabled. This alleviates the need to actually transfer the control from one TAP controller to the next. To maintain consistency with the IEEE JTAG recommendation, the TLM-based design is configured such that only one TAP is enabled upon reset. After reset, the TLM controls the multiply-enabled TAP controllers. Another specific example implementation is directed to a circuit control arrangement for such a multi-core IC having each TAP controller generate status and test signals in response to input signals directed to each of the multiple TAP controllers. A TAP link arrangement, including a TAP link module and control signals coupled to each of the multiple TAP controllers, selectively multiplexes the input signals to the multiple TAP controllers and multiplexes the status and test signals provided by the multiple TAP controllers to an output port of the IC.

Abstract translation: 一种安排控制一个设计有多个“核心”电路（如多个CPU）的IC，每个核心电路包括其自己的TAP控制器和一次启用多个TAP控制器。 对于通常要求在这种TAP控制器之间传输控制的应用，本发明的一个实施例配置基于TLM的设计，使得可以同时启用多个TAP控制器。 这减轻了将控制从一个TAP控制器实际传输到下一个的需要。 为了保持与IEEE JTAG建议的一致性，基于TLM的设计被配置为使得在复位时仅启用一个TA​​P。 复位后，TLM控制多功能TAP控制器。 另一个具体示例实现涉及用于这种多核IC的电路控制装置，其具有每个TAP控制器响应于针对多个TAP控制器中的每一个的输入信号而产生状态和测试信号。 包括TAP链路模块和耦合到多个TAP控制器中的每一个的控制信号的TAP链路布置选择性地将输入信号复用到多个TAP控制器，并将由多个TAP控制器提供的状态和测试信号复用到 IC。

公开(公告)号：US06438700B1

公开(公告)日：2002-08-20

申请号：US09313933

申请日：1999-05-18

Applicant: Swaroop Adusumilli

Inventor： Swaroop Adusumilli

IPC: G06F132

CPC classification number: G06F9/30189 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30181 ,  G06F9/3877 ,  Y02D10/128 ,  Y02D10/171

Abstract: The present invention is an ARM coprocessor power reduction system and method that turns off a coprocessor clock when an ARM system is performing THUMB state instructions. For example, the ARM coprocessor power reduction system and method of the present invention tracks signals from the ARM core periphery to determine if the ARM core is attempting to facilitate ARM state or THUMB state operations. The present invention compares the THUMB bit indicator in signals associated with each stage of an ARM pipeline and determines if the instructions are THUMB state instructions. If the instructions are THUMB state instructions the ARM coprocessor power reduction system and method of the present invention turns off the coprocessor clock. Turning off the coprocessor clock prevents the coprocessor registers from switching and consuming power. If an instruction fetched into an ARM pipeline is an ARM state instruction the ARM coprocessor power reduction system and method of the present invention turns the coprocessor clock back on.

Abstract translation: 本发明是一种在ARM系统执行THUMB状态指令时关闭协处理器时钟的ARM协处理器功率降低系统和方法。 例如，本发明的ARM协处理器功率降低系统和方法跟踪来自ARM内核外围的信号，以确定ARM核心是否正在尝试促进ARM状态或THUMB状态操作。 本发明比较了与ARM流水线的每一级相关联的信号中的THUMB位指示器，并确定指令是否是THUMB状态指令。 如果指令是THUMB状态指令，则本发明的ARM协处理器功率降低系统和方法关闭协处理器时钟。 关闭协处理器时钟可防止协处理器寄存器切换和消耗电力。 如果读取到ARM管线中的指令是ARM状态指令，则本发明的ARM协处理器功率降低系统和方法重新启动协处理器时钟。

公开(公告)号：US06311302B1

公开(公告)日：2001-10-30

申请号：US09283648

申请日：1999-04-01

Applicant: David Cassetti ,  James Steele ,  Swaroop Adusumilli

Inventor： David Cassetti ,  James Steele ,  Swaroop Adusumilli

IPC: G01R3128

CPC classification number: G01R31/318536

Abstract: An arrangement controls an IC designed with multiple “TLM'ed core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled a time. For applications typically requiring that control be transferred between such TAP controllers of various core circuits, one embodiment of the present invention expands a multiple “TLM'ed core” circuit design without changing the IEEE JTAG specification and without requiring more scan chains per TAP'ed core. One particular example embodiment includes each of the design's multiple cores including multiple test-access port (TAP) controllers, and including an internal TLM having a TLM register adapted to store a decodable instruction and a supplemental storage circuit adapted to store a coded signal. Also in the design, a chip-level TLM communicates with a common IEEE JTAG interface and with each of the multiple cores via the TLM register and the supplemental storage circuit. The chip-level TLM and the multiple cores signal use the supplemental storage circuit to indicate when instructions are to be transferred from a TLM'ed core to the chip-level TLM.

Abstract translation: 一种安排控制一个设计有多个“TLM”核心“电路的IC，如多个CPU，每个核心电路包括其自己的TAP控制器，并且启用了多个TAP控制器。 对于通常需要在各种核心电路的这种TAP控制器之间传输控制的应用，本发明的一个实施例扩展了多个“TLM”核心“电路设计而不改变IEEE JTAG规范，并且不需要每个TAP的更多的扫描链 核心。 一个具体示例性实施例包括设计的多个核心中的每一个，包括多个测试访问端口（TAP）控制器，并且包括具有适于存储可解码指令的TLM寄存器的内部TLM和适于存储编码信号的补充存储电路。 同样在设计中，芯片级TLM通过TLM寄存器和补充存储电路与普通的IEEE JTAG接口和多个内核中的每一个进行通信。 芯片级TLM和多核心信号使用补充存储电路来指示何时将指令从TLM的内核传送到芯片级的TLM。

公开(公告)号：US07072996B2

公开(公告)日：2006-07-04

申请号：US10172814

申请日：2002-06-12

Applicant: Swaroop Adusumilli ,  Satish N. Anand ,  Hemanshu Bhatnagar

Inventor： Swaroop Adusumilli ,  Satish N. Anand ,  Hemanshu Bhatnagar

IPC: G06F13/28

CPC classification number: G06F13/4031 ,  G06F13/28

Abstract: A flexible input/output (I/O) interface allows a processing core to communicate high-speed data with a several different types of interfaces including a Direct Memory Access (DMA) interface and a streaming interface. The I/O interface includes a streaming interface for transferring streamed data from the streaming data bus to the core-processing engine, a DMA interface for transferring DMA data from the DMA data bus to the core-processing engine, and an arbiter for coordinating data transfer with the core-processing engine between the streaming interface and DMA interface. The arbiter may operate in a split-bus-mode wherein the arbiter performs the address phase for more than one channel prior to entering into the data phase. The flexible I/O interface may include a common address bus and data bus between the processing engine and the interfaces. Alternatively, a switching fabric may couple separate address and data buss of the interfaces with the processing engine.

Abstract translation: 灵活的输入/输出（I / O）接口允许处理核心将高速数据与几种不同类型的接口进行通信，包括直接存储器访问（DMA）接口和流式接口。 I / O接口包括用于将流数据从流数据总线传送到核心处理引擎的流接口，用于将DMA数据从DMA数据总线传送到核心处理引擎的DMA接口，以及用于协调数据的仲裁器 在流接口和DMA接口之间与核心处理引擎进行传输。 仲裁器可以以分流总线模式操作，其中仲裁器在进入数据阶段之前执行多于一个通道的地址相位。 灵活的I / O接口可以包括处理引擎和接口之间的公共地址总线和数据总线。 或者，交换结构可以将接口的单独的地址和数据总线与处理引擎相耦合。

公开(公告)号：US06385749B1

公开(公告)日：2002-05-07

申请号：US09283809

申请日：1999-04-01

Applicant: Swaroop Adusumilli ,  James Steele ,  David Cassetti

Inventor： Swaroop Adusumilli ,  James Steele ,  David Cassetti

IPC: G01R3128

CPC classification number: G01R31/318563 ,  G01R31/318555

Abstract: An arrangement controls an IC designed with multiple “core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller. According to one example embodiment, multiple test-access port (TAP) controllers coupled to a common interface are controlled by adapting each TAP controller to receive input signals, determine if the TAP controller is enabled, and generate status signals and test signals. An output circuit responds to the TAP controllers by outputting one of the test signals respectively provided by the multiple TAP controllers, and a link module is used to maintain one of the TAP controllers enabled at a given time. The above-embodiment is useful, for example, in connection with IC applications that require an increasing number of core circuits without increasing the circuit area of the IC and/or the number of IC pins, and can be implemented to avoid changing existing structures of TAP controllers.

Abstract translation: 一种布置控制了设计有多个“核心”电路的IC，例如多个CPU，每个核心电路包括其自己的TAP控制器。 根据一个示例性实施例，耦合到公共接口的多个测试访问端口（TAP）控制器通过使每个TAP控制器适配以接收输入信号，确定TAP控制器是否被使能并产生状态信号和测试信号来控制。 输出电路通过输出由多个TAP控制器分别提供的一个测试信号来响应于TAP控制器，并且链路模块用于在给定时间内维持其中一个TAP控制器的使能。 上述实施例例如与需要越来越多的核心电路的IC应用有关，而不增加IC的电路面积和/或IC引脚的数量，并且可以实现以避免改变现有的结构 TAP控制器。